----------------------------------------------------------------------------------
-- Company:  University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    22:27:31 09/30/2007 
-- Design Name:    Pulser (Edge Detector)
-- Module Name:    pulser - Behavioral 
-- Description:    Simple module that produces a one clock-cycle pulse 
-- 						when triggered by a rising edge on the input signal.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pulser_db is
    Port ( Clk : in  STD_LOGIC;
			  D   : in  STD_LOGIC;
           Q   : out  STD_LOGIC;
           Qa_db : out  STD_LOGIC;
           Qb_db : out  STD_LOGIC
			  );
end pulser_db;

architecture Behavioral of pulser_db is

	signal Qa : STD_LOGIC; -- "future state"
	signal Qb : STD_LOGIC; -- "current state"
	
begin

	pulseexec : process (Clk,D,Qa)
	begin

		if (falling_edge(Clk)) then
			Qa <= D;
		else Qa <= Qa;
		end if;
		
		if (rising_edge(Clk)) then
			Qb <= Qa;
		else Qb <= Qb;
		end if;

	end process pulseexec;

	Q <= D and (not Qb);
	Qa_db <= Qa;
	Qb_db <= Qb;
	
end Behavioral;