----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    04:14:41 10/01/2007 
-- Design Name: 
-- Module Name:    WrMACaddrs - Behavioral 
-- Description:    Writes the first 12 bytes of a packet for transmission. 
--		   This constitutes writing source and destination MAC addresses
--		   from the 12 x 8bit MAC register.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;


entity WrMACaddrs is
    Port ( Clk : in  STD_LOGIC;
	   Rst : in STD_LOGIC;
	   Go : in STD_LOGIC;

	   MACregs_A  : out STD_LOGIC_VECTOR (3 downto 0);
	   MACregs_Q  : in STD_LOGIC_VECTOR (7 downto 0);

	   RAwrGo   : out STD_LOGIC;
	   --RAwrAddr : out STD_LOGIC_VECTOR (15 downto 0);
	   RAwrAinc : out STD_LOGIC;
	   RAwrD    : out STD_LOGIC_VECTOR (7 downto 0);
	   RAwrDone : in  STD_LOGIC;

	   Done : out STD_LOGIC;
	   db : out STD_LOGIC
	 );
end WrMACaddrs;

architecture Behavioral of WrMACaddrs is
	
	signal Data : STD_LOGIC_VECTOR (15 downto 0);
	--signal TxAddr : STD_LOGIC_VECTOR (15 downto 0);
	signal ByteCount : STD_LOGIC_VECTOR (3 downto 0);

--	signal Done_Byte : STD_LOGIC;
	signal Done_int : STD_LOGIC;
	signal En : STD_LOGIC;
	
	signal Go_NextByte : STD_LOGIC;
	signal Go_Wr : STD_LOGIC;
	signal PermitNextByte : STD_LOGIC;
	
begin

	MACregs_A <= ByteCount when En='1' else "ZZZZ";

	En_ctrl : process (Clk, Rst, Go, Done_int)
	begin
		if Rst = '1' then
			En <= '0';
		else
			if (Go='1') then
				En <= '1';
			else
				if falling_edge(Clk) and Done_int='1' then
					En <= '0';
				else
					En <= En;
				end if;
			end if;
		end if;
	end process;

	-- write MAC addresses from MAC register byte by byte

	RAwrGo 	<= Go_Wr;
	--RAwrAddr <= TxAddr when Go_Wr='1' else "ZZZZZZZZZZZZZZZZ";
	RAwrAinc <= '1' when Go_Wr='1' else 'Z';
	RAwrD <= MACregs_Q when Go_Wr='1' else "ZZZZZZZZ";
	--RAwrD	<= X"FF" when Go_Wr='1' else "ZZZZZZZZ";

	PermitNextByte <= RAwrDone and En and not (ByteCount(3) and ByteCount(1) and ByteCount(0));
	Done_int <= RAwrDone and En and ByteCount(3) and ByteCount(1) and ByteCount(0);
	--Done <= Done_int;
	u0: c_delay port map (Clk, Done_int, Done);
	
	u1: c_delay port map (Clk, PermitNextByte, Go_NextByte);
	--u1: Counter24bit port map (Clk, Rst, PermitNextByte, Go_NextByte);


	db <= Go_Wr;

	wrcontrol : process (Done_int, Go, Go_NextByte, ByteCount, Rst)
	begin
		if Rst='1' then
			Go_wr <= '0';
			ByteCount <= "0000";
			--TxAddr <= X"0000";
		else
			if (Go='1') then
				Go_Wr <= '1';
				ByteCount <= "0000";
				--TxAddr <= X"0000"; -- set to start of Tx buffer
			else
				Go_Wr <= Go_NextByte;
				--TxAddr <= X"F000"; -- codeword for "just increment from previous"

				if (rising_edge(Go_NextByte)) then
					ByteCount <= ByteCount + "0001";
				else
					ByteCount <= ByteCount;  
				end if;
			end if;
		end if;
	end process;

end Behavioral;