----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    04:14:41 10/01/2007 
-- Design Name: 
-- Module Name:    TxStatusCheck - Behavioral 
-- Description:    Checks the transmit status registers of the Eth. Ctrl.
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;


entity TxStatusCheck is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in STD_LOGIC;
           Go : in STD_LOGIC;
			  Done : out STD_LOGIC;
			  
			-- Transceiver control lines
			  TxRx_Go : out  STD_LOGIC;
           TxRx_RiW : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
			  TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0);
           TxRx_Done : in  STD_LOGIC;

			-- Serial log output lines
 			  ser_Go : out STD_LOGIC;
  			  ser_D : out STD_LOGIC_VECTOR (7 downto 0);
			  db : out STD_LOGIC
			);
end TxStatusCheck;

architecture Behavioral of TxStatusCheck is
	
	signal Go_r : STD_LOGIC;
	signal Go_read : STD_LOGIC;
	signal Go_late : STD_LOGIC;
	signal Go_read_delayed : STD_LOGIC;
	signal Done_read : STD_LOGIC;
	signal Done_regs1 : STD_LOGIC;
	signal Done_regs2 : STD_LOGIC;
	signal Done_regs3 : STD_LOGIC;
	signal Finished : STD_LOGIC;
	signal Data : STD_LOGIC_VECTOR (7 downto 0);
	signal Addr : STD_LOGIC_VECTOR (7 downto 0);
	signal Cnt : STD_LOGIC_VECTOR (7 downto 0);
	signal AddrCur : STD_LOGIC_VECTOR (7 downto 0);

begin

	u0: Counter24bit port map (Clk, Rst, Go, Go_late);
	--u0: c_delay port map (Clk, Go, Go_late);
	--Go_late <= Go;
	Go_r <= Go_late or (Done_read and not Finished);

	u: Counter21bit port map (Clk, Rst, Go_r, Go_read);

	u1: getByte port map (Clk, Rst, Go_read, Addr, Data, Done_read,
						TxRx_Go, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done);
	u2: c_delay port map (Clk, Go_read, Go_read_delayed);

--	ser_Go <= Go or Go_read or Done_regs3;
--	ser_D <= X"2D" when Go='1' else
--				AddrCur when Go_read='1' else
--				X"2E"	when Done_regs3='1' else
--				"ZZZZZZZZ";
	
	ser_Go <= Go or Done_read or Done_regs3;
	ser_D <= X"2D" when Go='1' else
				TxRx_Q when Done_read='1' else
				X"2E"	when Done_regs3='1' else
				"ZZZZZZZZ";


	-- Done delay chain in order to send the termination code: 0x2E
	--  for the literal status register value sequence
	Done_regs1 <= Finished and Done_read;
	u3: c_delay port map (Clk, Done_regs1, Done_regs2);
	u4: c_delay port map (Clk, Done_regs2, Done_regs3);
	Done <= Done_regs3;

	-- Tx status register address shuffle control
	proc : process (Clk, Go, Rst, Go_read_delayed, Go_read) begin
		if Rst='1' then 
			Finished <= '0';	Cnt <= X"5A";
		else
			if Go_late='1' then
				Cnt <= X"57"; -- set address pointer to first Tx status reg.
				Finished <= '0';
			else
				if falling_edge(Clk) then
					if Go_read_delayed='1' then 
						if Cnt=X"62" then
							Finished <= '1';
						else
							Cnt <= Cnt + X"01";
						end if;
					else
						if Go_read='1' then 
							AddrCur <= Cnt;
						end if;
					end if;
				end if;	
			end if;
		end if;
	
		case Cnt is
--			when X"5A" => Addr <= X"53"; --TXCN
			when X"5B" => Addr <= X"78"; --PHYCN
			--when X"5C" => Addr <= X"54"; --TXBUSY
			when others => Addr <= Cnt;
		end case;
	
	end process;
	
end Behavioral;