----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    04:14:41 10/01/2007 
-- Design Name: 
-- Module Name:    TxBufCheck - Behavioral 
-- Description:    Checks the transmit buffer
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;


entity TxBufCheck is
    Port ( Clk : in  STD_LOGIC;
	   Rst : in STD_LOGIC;
           Go : in STD_LOGIC;
	   Done : out STD_LOGIC;
			  
	   -- Transceiver control lines
	   TxRx_Go : out  STD_LOGIC;
           TxRx_RiW : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
	   TxRx_D : out STD_LOGIC_VECTOR (7 downto 0);
	   TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0);
           TxRx_Done : in  STD_LOGIC;

	   -- Serial log output lines
 	   ser_Go : out STD_LOGIC;
  	   ser_D : out STD_LOGIC_VECTOR (7 downto 0);
	   db : out STD_LOGIC
	 );
end TxBufCheck;

architecture Behavioral of TxBufCheck is
	
	signal Go_NextByte : STD_LOGIC;
	signal Go_ChAddr : STD_LOGIC;
	signal Done_read : STD_LOGIC;
	signal Done_Addr : STD_LOGIC;
	signal Data : STD_LOGIC_VECTOR (7 downto 0);
	signal RAaddr : STD_LOGIC_VECTOR (15 downto 0);

	signal TxRx_Go_ra1 : STD_LOGIC;
	signal TxRx_Go_ra2 : STD_LOGIC;
begin

	u0: Counter21bit port map (Clk, Rst, Go_NextByte, Go_ChAddr);

	-- move pointer: write RAMADDRH (0x08) and RAMADDRL (0x09) (latter implied) 
	ra1: wr2BToAddr
	port map (Clk, Rst, Go_ChAddr, X"08", RAaddr, 
		  TxRx_Go_ra1, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_Addr);

	-- Get data from Tx register byte with above-specified address
	ra2: getByte
	port map (Clk, Rst, Done_Addr, X"04", Data, Done_read,
		  TxRx_Go_ra2, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done);
						
	-- Increment Tx buffer address
	procaddr: process (Clk,	Go_NextByte)
	begin
		if Go='1' then
			RAaddr <= X"0000";
		else
			if falling_edge(Clk) and Go_NextByte = '1' then
				RAaddr <= RAaddr + X"0001";
			else
				RAaddr <= RAaddr;
			end if;
		end if;
	end process;
	
	Go_NextByte <= '0' when RAaddr=X"07FF" else (Go or Done_read) ;
	Done <= Done_read when RAaddr=X"07FF" else '0';
						
	ser_Go <= Go or Done_read;
	ser_D <= X"2F" when Go='1' else
		 TxRx_Q when Done_read='1' else
		 --RAaddr(7 downto 0) when Done_read='1' else
		 --X"2E"	when Done_regs3='1' else
		 "ZZZZZZZZ";

	TxRx_Go <= TxRx_Go_ra1 or TxRx_Go_ra2;
	
end Behavioral;