---------------------------------------------------------------------------------- -- Company: University of Connecticut -- Engineer: Igor Senderovich -- -- Create Date: 04:14:41 10/01/2007 -- Design Name: -- Module Name: Transmitter_ctrl - Behavioral -- Description: Assembles a packet D or S packet for transmission using -- the Transceiver. ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library FPGA_BasicComp; use FPGA_BasicComp.BasicComp.all; entity Transmitter is Port ( Clk : in STD_LOGIC; Rst : in STD_LOGIC; state_En : out STD_LOGIC; state_D : out STD_LOGIC_VECTOR (2 downto 0); state_Q : in STD_LOGIC_VECTOR (2 downto 0); LocStamp : in STD_LOGIC_VECTOR (7 downto 0); --PktNum : in STD_LOGIC_VECTOR (15 downto 0); MACregs_A : out STD_LOGIC_VECTOR (3 downto 0); MACregs_Q : in STD_LOGIC_VECTOR (7 downto 0); TempReg_Q : in STD_LOGIC_VECTOR (15 downto 0); ADCReg_Addr : out STD_LOGIC_VECTOR (2 downto 0); ADCReg_Q : in STD_LOGIC_VECTOR (15 downto 0); DACReg_Addr : out STD_LOGIC_VECTOR (4 downto 0); DACReg_Q : in STD_LOGIC_VECTOR (15 downto 0); TxRx_Go : out STD_LOGIC; TxRx_RiW : out STD_LOGIC; TxRx_A : out STD_LOGIC_VECTOR (7 downto 0); TxRx_D : out STD_LOGIC_VECTOR (7 downto 0); TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0); TxRx_Done : in STD_LOGIC; --Interrupt catcher control lines INT_Go : out STD_LOGIC; INT_Mask : out STD_LOGIC_VECTOR (7 downto 0); INT_Found : in STD_LOGIC_VECTOR (7 downto 0); INT_Done : in STD_LOGIC; ser_Go : out STD_LOGIC; ser_D : out STD_LOGIC_VECTOR (7 downto 0); db : out STD_LOGIC ); end Transmitter; architecture Behavioral of Transmitter is component AwaitClearLink is Port ( Clk : in STD_LOGIC; Rst : in STD_LOGIC; Go : in STD_LOGIC; Done : out STD_LOGIC; TxRx_Go : out STD_LOGIC; TxRx_RiW : out STD_LOGIC; TxRx_A : out STD_LOGIC_VECTOR (7 downto 0); TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0); TxRx_Done : in STD_LOGIC; ser_Go : out STD_LOGIC; ser_D : out STD_LOGIC_VECTOR (7 downto 0); db : out STD_LOGIC ); end component; component DPacket is Port ( Clk : in STD_LOGIC; Rst : in STD_LOGIC; Go : in STD_LOGIC; LocStamp : in STD_LOGIC_VECTOR (7 downto 0); DACReg_Addr : out STD_LOGIC_VECTOR (4 downto 0); DACReg_Q : in STD_LOGIC_VECTOR (15 downto 0); RAwrGo : out STD_LOGIC; RAwrAddr : out STD_LOGIC_VECTOR (15 downto 0); RAwrD : out STD_LOGIC_VECTOR (7 downto 0); RAwrDone : in STD_LOGIC; TxRx_Go : out STD_LOGIC; TxRx_RiW : out STD_LOGIC; TxRx_A : out STD_LOGIC_VECTOR (7 downto 0); TxRx_D : out STD_LOGIC_VECTOR (7 downto 0); TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0); TxRx_Done : in STD_LOGIC; Done : out STD_LOGIC; db : out STD_LOGIC ); end component; component SPacket is Port ( Clk : in STD_LOGIC; Rst : in STD_LOGIC; Go : in STD_LOGIC; LocStamp : in STD_LOGIC_VECTOR (7 downto 0); PktNum : in STD_LOGIC_VECTOR (15 downto 0); TempReg_Q : in STD_LOGIC_VECTOR (15 downto 0); ADCReg_Addr : out STD_LOGIC_VECTOR (2 downto 0); ADCReg_Q : in STD_LOGIC_VECTOR (15 downto 0); RAwrGo : out STD_LOGIC; RAwrAddr : out STD_LOGIC_VECTOR (15 downto 0); RAwrD : out STD_LOGIC_VECTOR (7 downto 0); RAwrDone : in STD_LOGIC; TxRx_Go : out STD_LOGIC; TxRx_RiW : out STD_LOGIC; TxRx_A : out STD_LOGIC_VECTOR (7 downto 0); TxRx_D : out STD_LOGIC_VECTOR (7 downto 0); TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0); TxRx_Done : in STD_LOGIC; Done : out STD_LOGIC; ser_Go : out STD_LOGIC; ser_D : out STD_LOGIC_VECTOR (7 downto 0) ); end component; component TxStatusCheck is Port ( Clk : in STD_LOGIC; Rst : in STD_LOGIC; Go : in STD_LOGIC; Done : out STD_LOGIC; -- Transceiver control lines TxRx_Go : out STD_LOGIC; TxRx_RiW : out STD_LOGIC; TxRx_A : out STD_LOGIC_VECTOR (7 downto 0); TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0); TxRx_Done : in STD_LOGIC; -- Serial log output lines ser_Go : out STD_LOGIC; ser_D : out STD_LOGIC_VECTOR (7 downto 0); db : out STD_LOGIC ); end component; component TxBufCheck is Port ( Clk : in STD_LOGIC; Rst : in STD_LOGIC; Go : in STD_LOGIC; Done : out STD_LOGIC; -- Transceiver control lines TxRx_Go : out STD_LOGIC; TxRx_RiW : out STD_LOGIC; TxRx_A : out STD_LOGIC_VECTOR (7 downto 0); TxRx_D : out STD_LOGIC_VECTOR (7 downto 0); TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0); TxRx_Done : in STD_LOGIC; -- Serial log output lines ser_Go : out STD_LOGIC; ser_D : out STD_LOGIC_VECTOR (7 downto 0); db : out STD_LOGIC ); end component; component WrMACaddrs is Port ( Clk : in STD_LOGIC; Rst : in STD_LOGIC; Go : in STD_LOGIC; MACregs_A : out STD_LOGIC_VECTOR (3 downto 0); MACregs_Q : in STD_LOGIC_VECTOR (7 downto 0); RAwrGo : out STD_LOGIC; --RAwrAddr : out STD_LOGIC_VECTOR (15 downto 0); RAwrAinc : out STD_LOGIC; RAwrD : out STD_LOGIC_VECTOR (7 downto 0); RAwrDone : in STD_LOGIC; Done : out STD_LOGIC; db : out STD_LOGIC ); end component; signal Data : STD_LOGIC_VECTOR (7 downto 0); signal Len2B : STD_LOGIC_VECTOR (15 downto 0); signal InitGo, En, Go_TxStart0, Go_TxD, Go_TxS, Go_TxStart : STD_LOGIC; signal Done_DPacket, Done_SPacket, Done_TxStart1, Done_TxStart2 : STD_LOGIC; signal Done_Send, Done_Addr, Done_MAC, Done_Len, Done_INTcatch : STD_LOGIC; signal MACregs_A_int : STD_LOGIC_VECTOR (3 downto 0); -- Signals for RAwrToAddr module single instantiation signal RAwrAddr : STD_LOGIC_VECTOR (15 downto 0); signal RAwrD : STD_LOGIC_VECTOR (7 downto 0); signal RAwrDone, RAwrGo, RAwrGo_uTxMAC, RAwrGo_uTxLen, RAwrGo_uSpack, RAwrGo_uDpack : STD_LOGIC; -- TxRx_Go bus lines signal TxRx_Go_u0, TxRx_Go_u2, TxRx_Go_uTxS2, TxRx_Go_uTxSt1, TxRx_Go_aH : STD_LOGIC; signal TxRx_Go_uSpack, TxRx_Go_uDpack, TxRx_Go_uCheck1, TxRx_Go_uSend : STD_LOGIC; signal TxRx_Go_uCheck2, TxRx_Go_ACL, TxRx_Go_ACL2, TxRx_Go_RxInh1, TxRx_Go_RxInh2 : STD_LOGIC; signal RAwrToAddr_db, wrMACaddrs_db : STD_LOGIC; -- RAwrToAddr stuff signal RAwrAddr_reg : STD_LOGIC_VECTOR (15 downto 0); signal RAwr_data : STD_LOGIC_VECTOR (7 downto 0); -- states/pulses signal RAwrGo_late : STD_LOGIC; signal Go_ChState : STD_LOGIC; signal Done_TxStatCheck : STD_LOGIC; signal Done_TxBufCheck : STD_LOGIC; signal ser_Go_uCheck1, ser_Go_uCheck2, ser_Go_ACL, ser_Go_ACL2, ser_Go_uSpack : STD_LOGIC; signal LineClear, LineClear2 : STD_LOGIC; signal PktNum : STD_LOGIC_VECTOR (15 downto 0); begin En <= state_Q(2) and state_Q(0); -- Define InitGo --u1: pulser port map (Clk, En, InitGo); u1: Pulse_Delay port map (Clk, En, InitGo); -- u2: AwaitClearLink -- port map (Clk, Rst, InitGo, LineClear, -- TxRx_Go_ACL, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done, ser_Go_ACL,ser_D); -- LineClear <= InitGo; -- Temporarily inhibit packet reception uRxInh1: wrToAddr port map (Clk, Rst, InitGo, X"11", "00001000", TxRx_Go_RxInh1, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, LineClear); --uu: Counter21bit port map (Clk, Rst, LineClear, Go_TxStart); Go_TxStart <= LineClear; -- put TXSTARTH (0x59) and TXSTARTL (0x5A) at 0x0000 location in Tx buffer uTxSt1: wr2BtoAddr port map (Clk, Rst, Go_TxStart, X"59", X"0000", TxRx_Go_uTxSt1, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_TxStart1); ADCReg_Addr <= "000" when Go_TxStart='1' else "ZZZ"; --------------------------------------------------------------------------------- -- Inlining RAwrToAddr ---------------------------------------------------------- RAwr_u1: c_delay port map (Clk, RAwrGo, RAwrGo_late); --RAwr_u1: Counter16bit port map (Clk, Rst, RAwrGo, RAwrGo_late); -- move pointer: write RAMADDRH (0x08) and RAMADDRL (0x09) (latter implied) RAwr_aH: wr2BToAddr port map (Clk, Rst, RAwrGo_late, X"08", RAwrAddr_reg, TxRx_Go_aH, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_Addr); -- write data to RAMTXDATA (0x04) on RAMAddrL write completion RAwr_u2: wrToAddr port map (Clk, Rst, Done_Addr, X"04", RAwr_data, TxRx_Go_u2, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, RAwrDone); RAwr_r1: Reg8bit port map (Clk, Rst, RAwrGo, RAwrD, RAwr_data); -- Latch RAM addr. or increment previous value if addr. MSB is '1' procaddr: process (Clk, RAwrGo, RAwrAddr) begin if Rst='1' or Go_TxStart='1' then RAwrAddr_reg <= X"0000"; else if falling_edge(Clk) then if RAwrGo = '1' and RAwrAddr(15)='0' then RAwrAddr_reg <= RAwrAddr; elsif Done_Addr='1' then RAwrAddr_reg <= RAwrAddr_reg + X"0001"; end if; end if; end if; end process; ------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------ RAwrGo <= RAwrGo_uTxMAC or RAwrGo_uTxLen or RAwrGo_uSpack or RAwrGo_uDpack; -- write MAC addresses uTxMAC: wrMACaddrs port map (Clk, Rst, Done_TxStart1, MACregs_A, MACregs_Q, RAwrGo_uTxMAC, RAwrAddr(15), RAwrD, RAwrDone, Done_MAC, wrMACaddrs_db); --MACregs_A <= MACregs_A_int when En = '1' else "ZZZZ"; --write packet type -- Len2B <= X"08FF"; -- -- uTxLen: RAwr2BtoAddr -- port map (Clk, Rst, Done_MAC, X"F000", Len2B, -- RAwrGo_uTxLen, RAwrAddr, RAwrD, RAwrDone, Done_Len); -- w1: Counter24bit port map (Clk, Rst, Done_MAC, Go_TxS); Go_TxD <= Done_MAC and state_Q(1); Go_TxS <= Done_MAC and not state_Q(1); uPktNum: StepCounter16bit port map (Clk, Rst, Done_MAC, PktNum); uDpack: DPacket port map (Clk, Rst, Go_TxD, LocStamp, DACReg_Addr, DACReg_Q, RAwrGo_uDpack, RAwrAddr, RAwrD, RAwrDone, TxRx_Go_uDpack,TxRx_RiW,TxRx_A,TxRx_D,TxRx_Q,TxRx_Done, Done_DPacket, db); uSpack: SPacket port map (Clk, Rst, Go_TxS, LocStamp, PktNum, TempReg_Q, ADCReg_Addr, ADCReg_Q, RAwrGo_uSpack, RAwrAddr, RAwrD, RAwrDone, TxRx_Go_uSpack,TxRx_RiW, TxRx_A,TxRx_D,TxRx_Q,TxRx_Done,Done_SPacket, ser_Go_uSpack,ser_D); Go_TxStart0 <= Done_DPacket or Done_SPacket; -- Repeat task above at uTxSt1 uTxS2: wr2BtoAddr port map (Clk, Rst, Go_TxStart0, X"59", X"0000", TxRx_Go_uTxS2, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_TxStart2); -- u3: AwaitClearLink -- port map (Clk, Rst, Done_TxStart2, LineClear2, -- TxRx_Go_ACL2, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done, -- ser_Go_ACL2, ser_D); LineClear2<=Done_TxStart2; -- Send packet! uSend: wrToAddr port map (Clk, Rst, LineClear2, X"53", "00111011", TxRx_Go_uSend, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_Send); -- uCheck1: InspectReg -- port map (Clk, Rst, Done_Send, X"78", Done_TxStatCheck, -- TxRx_Go_uCheck1, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done, -- ser_Go_uCheck1, ser_D); -- -- uCheck2: InspectReg -- port map (Clk, Rst, Done_TxStatCheck, X"80", Done_TxBufCheck, -- TxRx_Go_uCheck2, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done, -- ser_Go_uCheck2, ser_D); -- uCheck1: TxStatusCheck -- port map (Clk, Rst, Done_Send, Done_TxStatCheck, -- TxRx_Go_uCheck1, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done, -- ser_Go_uCheck1, ser_D); -- uCheck2: TxBufCheck -- port map (Clk, Rst, Done_TxStatCheck, Done_TxBufCheck, -- TxRx_Go_uCheck2, TxRx_RiW, TxRx_A, TxRx_D, TxRx_Q, TxRx_Done, -- ser_Go_uCheck2, ser_D); --INT_Go <= Done_Send; INT_Mask <= "ZZZZZZZZ";--;"00100000" when Done_Send='1' else "ZZZZZZZZ"; -- t1: Trigger port map (Rst, Done_Send, INT_Done, Done_INTcatch); Done_INTcatch <= Done_Send; --u5: c_delay port map (Clk, Done_INTcatch, Go_ChState); --u5: Counter16bit port map (Clk, Rst, Done_INTcatch, Go_ChState); --u5: Counter21bit port map (Clk, Rst, InitGo, Go_ChState); --Go_ChState <= Done_INTcatch; -- Turn packet reception back on uRxInh2: wrToAddr port map (Clk, Rst, Done_INTcatch, X"11", "00000000", TxRx_Go_RxInh2, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Go_ChState); state_En <= Go_ChState; state_D <= "010" when Go_ChState='1' else "ZZZ"; TxRx_Go <= En and (TxRx_Go_RxInh1 or TxRx_Go_RxInh2 or TxRx_Go_ACL2 or TxRx_Go_ACL or TxRx_Go_aH or TxRx_Go_u2 or TxRx_Go_uSend or TxRx_Go_uTxS2 or TxRx_Go_uSpack or TxRx_Go_uDpack or TxRx_Go_uTxSt1 or TxRx_Go_u0 or TxRx_Go_uCheck1 or TxRx_Go_uCheck2); ser_Go <= --ser_Go_uSpack or ser_Go_uCheck1 or ser_Go_uCheck2 --ser_Go_ACL or ser_Go_ACL2 ;-- or ser_Go_ACL or ser_Go_ACL2;-- or Done_TxStart1; --TxRx_Go_u2 or ; -- ser_D <= RAwr_data when Done_Addr='1' else "ZZZZZZZZ"; -- ser_D <= --RAwr_data when TxRx_Go_u2='1' else -- X"2D" when Done_TxStart1='1' else "ZZZZZZZZ"; --ser_D <= ADCReg_Q(7 downto 0) when LineClear='1' else "ZZZZZZZZ"; ser_D <= "ZZZZZZZZ"; end Behavioral;