----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    04:14:41 10/01/2007 
-- Design Name: 
-- Module Name:    S-Packet - Behavioral 
-- Description:    Assembles S-type packet - DAC values
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity SPacket is
    Port ( Clk : in  STD_LOGIC;
	   Rst : in STD_LOGIC;
	   Go : in STD_LOGIC;

	   LocStamp : in STD_LOGIC_VECTOR (7 downto 0);

	   TempReg_Q : in  STD_LOGIC_VECTOR (15 downto 0);
	   ADCReg_Addr : out  STD_LOGIC_VECTOR (2 downto 0);
           ADCReg_Q : in  STD_LOGIC_VECTOR (15 downto 0);

	   RAwrGo   : out STD_LOGIC;
	   RAwrAddr : out STD_LOGIC_VECTOR (15 downto 0);
	   RAwrD    : out STD_LOGIC_VECTOR (7 downto 0);
	   RAwrDone : in  STD_LOGIC;

           TxRx_Go : out  STD_LOGIC;
           TxRx_RiW : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0);
           TxRx_Done : in  STD_LOGIC;

	   Done : out STD_LOGIC
	 );
end SPacket;

architecture Behavioral of SPacket is
	
	component RAwr2BtoAddr is
	    Port ( Clk : in  STD_LOGIC;
		   Rst : in STD_LOGIC;
		   Go : in STD_LOGIC;
		   RamAddr : in STD_LOGIC_VECTOR (15 downto 0); -- AddrH:AddrL
		   D : in STD_LOGIC_VECTOR (15 downto 0);        -- Data
		   RAwrGo   : out STD_LOGIC;
		   RAwrAddr : out STD_LOGIC_VECTOR (15 downto 0);
		   RAwrD    : out STD_LOGIC_VECTOR (7 downto 0);
		   RAwrDone : in  STD_LOGIC;
		   Done : out STD_LOGIC
		 );
	end component;

	signal Data : STD_LOGIC_VECTOR (15 downto 0);
	--signal TxAddr : STD_LOGIC_VECTOR (15 downto 0);
	signal ChanCount : STD_LOGIC_VECTOR (5 downto 0);

	signal Done_Word : STD_LOGIC;-- := '0';
	signal Go_NextWord : STD_LOGIC;
	signal Go_Wr : STD_LOGIC;
	signal Go_TxEnd : STD_LOGIC;
	signal PermitNextWord : STD_LOGIC;
	signal En : STD_LOGIC;-- := '0';

begin
	
	-- write 2-byte word ('1' in MSB of addr just means increment from prev.)
	w: RAwr2BtoAddr
	port map (Clk, Rst, Go_Wr, X"F000", Data, 
		  RAwrGo, RAwrAddr, RAwrD, RAwrDone,
		  --TxRx_Go, TxRx_Aout, TxRx_Dout, TxRx_RiW, TxRx_Done, 
		  Done_Word);
						
	PermitNextWord <= Done_Word and En;
	u1: c_delay port map (Clk, PermitNextWord, Go_NextWord);
	Go_Wr <= Go or Go_NextWord;	

	ADCReg_Addr <= ChanCount(2 downto 0) when En='1' else "ZZZ";
	
	Go_TxEnd <= Done_Word and not En;

	-- pad to 46 bytes by setting TXENDH (0x57) & TXENDL (0x58) to 0x0040 
	uTxSt1: wr2BtoAddr
	port map (Clk, Rst, Go_TxEnd, X"57", X"0040", 
		  TxRx_Go, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done);

	wrcontrol : process (Done_Word,Go,Go_NextWord,ChanCount,LocStamp)
	begin
		if (Go='1') then
			Data <= LocStamp & X"53";	-- start packet payload with loc. and 'S'
			En <='1';
			--TxAddr <= X"0000";        -- beginning of Tx Buffer
			ChanCount <= "001001";
		else
			if (ChanCount(3)='1') then
				Data <= TempReg_Q;
			else
				Data <= ADCReg_Q;
			end if;
			
			--TxAddr <= X"F000"; -- codeword for "just increment from previous"

			if (rising_edge(Done_Word)) then
				--if (ChanCount="001010") then
				if (ChanCount="000000") then
					En <= '0';
					ChanCount <= ChanCount;
				else
					En <= En; 
					ChanCount <= ChanCount - "000001";
				end if;
			else
				ChanCount <= ChanCount;  En <= En;
			end if;
	
		end if;
	
	end process;


end Behavioral;