----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    04:14:41 10/01/2007 
-- Design Name: 
-- Module Name:    AwaitClearLink_ctrl - Behavioral 
-- Description:    Assembles a packet D or S packet for transmission using 
--		   the Transceiver.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;


entity AwaitClearLink is
    Port ( Clk : in  STD_LOGIC;
	   Rst : in STD_LOGIC;
	   Go : in STD_LOGIC;
	   Done : out STD_LOGIC;

           TxRx_Go : out  STD_LOGIC;
           TxRx_RiW : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
	   TxRx_Q : in STD_LOGIC_VECTOR (7 downto 0);
           TxRx_Done : in  STD_LOGIC;

 	   ser_Go : out STD_LOGIC;
  	   ser_D : out STD_LOGIC_VECTOR (7 downto 0);
	   db : out STD_LOGIC
	 );
end AwaitClearLink;

architecture Behavioral of AwaitClearLink is
	
	signal Data : STD_LOGIC_VECTOR (7 downto 0);
	
	signal TxRx_Go_bz : STD_LOGIC;		
	signal TxRx_Go_an1 : STD_LOGIC;
	signal TxRx_Go_an2 : STD_LOGIC;
	

	signal Done_BusyWait : STD_LOGIC;
	signal Go_ChkBusy : STD_LOGIC;
	signal Done_ChkBusy : STD_LOGIC;
	signal Go_BZidle : STD_LOGIC;
	signal Done_BZidle : STD_LOGIC;
	signal Go_ANidle : STD_LOGIC;
	signal Done_ANidle : STD_LOGIC;
	signal Go_ChkAN : STD_LOGIC;
	signal Done_ChkAN : STD_LOGIC;
	signal Done_ANWait : STD_LOGIC;
	signal Done_ChkLnk :STD_LOGIC;
	signal Go_ChkLnk :STD_LOGIC;

begin

	-- Idle if Tx interface is busy ------------------------------
	Go_ChkBusy <= Go or Done_BZidle;
		
	bz1: getByte
	port map (Clk, Rst, Go_ChkBusy, X"54", Data, Done_ChkBusy,
		  TxRx_Go_bz, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done);

	bz2: Counter16bit port map (Clk, Rst, Go_BZidle, Done_BZidle);
	Go_BZidle <= Done_ChkBusy and Data(0);

	Done_BusyWait <= Done_ChkBusy and not Data(0);

	------------------------------------------------------------

	-- Idle if link is not properly negotiated--------------------
	Go_ChkAN <= Done_BusyWait or Done_ANidle;
		
	an1: getByte
	port map (Clk, Rst, Go_ChkAN, X"80", Data, Done_ChkAN,
		  TxRx_Go_an1, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done);

	an2: getByte
	port map (Clk, Rst, Go_ChkLnk, X"78", Data, Done_ChkLnk,
		  TxRx_Go_an2, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done);

	an3: Counter21bit port map (Clk, Rst, Go_ANidle, Done_ANidle);

	Go_ANidle <= '1' when (Done_ChkAN='1' and Data/=X"00") or 
			(Done_ChkLnk='1' and Data(0)='0') else '0';

	Go_ChkLnk <= '1' when (Done_ChkAN='1' and Data=X"00") else '0';
	Done_ANWait <= '1' when (Done_ChkLnk='1' and Data(0)='1') else '0';
	------------------------------------------------------------

	Done <= Done_ANWait;
	
	TxRx_Go <= TxRx_Go_bz or TxRx_Go_an1 or TxRx_Go_an2;
	ser_Go <= Done_ChkAN or Done_ChkLnk or Go_BZidle or Go_ANidle;
	ser_D <= Data when (Done_ChkAN or Done_ChkLnk)='1' else 
		 X"2F" when (Go_ANidle or Go_BZidle)='1' else "ZZZZZZZZ";
	
end Behavioral;