----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    04:14:41 10/01/2007 
-- Module Name:    Transceiver_ctrl - Behavioral 
-- Description:	   Intermediate component between FPGA internal modules and the  
--		   Ethernet Contoller Chip (Eth) Translates requests into 
-- 		   Multiplexed Intel bus format and mediates the clock subdivision 
-- Description:	   between Eth 20MHz clock and FPGA internal 5MHz clock.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity Transceiver is
    Port ( fClk : in  STD_LOGIC; -- "fast" clock of the EthCtrl
	   sClk : out STD_LOGIC;
	   Rst : in STD_LOGIC;

	   -- MuxIntel lines ------------------------
	   ALE : out STD_LOGIC;
	   AD  : inout STD_LOGIC_VECTOR (7 downto 0);
	   iRD : out STD_LOGIC;
	   iWR : out STD_LOGIC;

	   -- FPGA-Internal input lines -------------
           TxRx_Go : in  STD_LOGIC;
           TxRx_RiW : in  STD_LOGIC;
           TxRx_A : in  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : in  STD_LOGIC_VECTOR (7 downto 0);

	   TxRx_Q : out STD_LOGIC_VECTOR (7 downto 0);
           TxRx_Done : out  STD_LOGIC;
	   TxRx_db : out STD_LOGIC
	 );
end Transceiver;

architecture Behavioral of Transceiver is
	
	signal CLK0 : STD_LOGIC;
	signal sClk_int : STD_LOGIC;

--	signal TickCount : STD_LOGIC_VECTOR (1 downto 0);
	signal count : STD_LOGIC_VECTOR (3 downto 0);
	signal En_Convo : STD_LOGIC;
	signal TxRx_AlmostDone : STD_LOGIC;
	signal TxRx_Working : STD_LOGIC;
	
	signal Dout : STD_LOGIC_VECTOR (7 downto 0);
	signal Addr : STD_LOGIC_VECTOR (7 downto 0);
	signal RWflag : STD_LOGIC;
	signal RiW_int : STD_LOGIC;
	signal fGo : STD_LOGIC;
	
begin

	-- Clock subdivision (1/4th the frequency) ----------------
--	sClk_int <= TickCount(1);
--	sClk <= sClk_int;
--	sCLKsubdiv : process (fClk,TickCount)
--	begin
--		if (Rst='1') then
--			TickCount <= "00";
--		else
--			if (rising_edge(fClk)) then
--				TickCount <= TickCount + "01";
--			else
--				TickCount <= TickCount;
--			end if;
--		end if;
--
--	end process;
	-----------------------------------------------------------

	--Xilinx primitive for use of dedicated clock resources
	DCM_SP_inst : DCM_SP
	generic map (CLKDV_DIVIDE => 4.0)
	port map (
		RST => Rst, -- 1-bit The reset input pin (RST) resets the DCM circuitry. The RST signal is an
		CLKIN => fClk, -- 1-bit Clock input for the DCM.
		CLK0 => CLK0,  -- 1-bit Same frequency as CLKIN, 0 degree phase shift.
		CLKFB => CLK0, -- Clock feedback
		CLKDV => sClk_int -- Divided clock
	);
	sClk <= sClk_int;

	TxRx_db <= Addr(2);
	-- Trim 5MHz-based TxRx_Go for latching on 20MHz clock
	u1: pulser port map (fClk, TxRx_Go, fGo);
	
	-- Conversation process "metronome"
	u2: EdgeCounter4bit port map (fClk, Rst, TxRx_Go, En_Convo, count);
	
	-- send "Done" two cycles after "Go
	u3: c_delay port map (sClk_int, TxRx_Go, TxRx_Working);
	--u4: c_delay port map (sClk_int, TxRx_Working, TxRx_AlmostDone);
	u5: c_delay port map (sClk_int, TxRx_Working, TxRx_Done);

	
	ALE <= not (count(3) or count(2) or count(1));
		
	-- Intel bus conversation schedule ------------------------------
	ConvoTiming : process (fClk, Rst, RiW_int, TxRx_RiW, count, Addr, Dout)
	begin
		if (Rst='1') then
			RiW_int <= '0';
			TxRx_Q <= X"00";
			AD <= "ZZZZZZZZ";
		else
			case count is -- | R/W flags    | Data&Addr I/O |
				when "0000" =>
					RWflag <= '1';
					AD <= X"00";  	
				when "0001" =>
					RWflag <= '1';
					AD <= Addr;		
				when "0010" =>
					RWflag <= '1';
					AD <= Addr;		
				when "0011" =>
					RWflag <= '1';
					AD <= Addr;		
				when "0100" =>
					RWflag <= '1';
					AD <= Addr;		
				when "0101" =>
					RWflag <= '1';
					AD<="ZZZZZZZZ";
				when "1000" =>
					RWflag <= '0';
					if RiW_int='0' then
						AD <= Dout;	
					else
						AD<="ZZZZZZZZ";
					end if;
				when "1101" =>
					RWflag <= '1';
					AD<="ZZZZZZZZ";
					--if (RiW_int='1') then
					--	 TxRx_Dout <= AD;
					--end if;
				when "1110" =>
					RWflag <= '1';
					AD<="ZZZZZZZZ";
				when "1111" =>
					RWflag <= '1';
					AD<="ZZZZZZZZ";
					--if (RiW_int='0') then
					--	AD <= "ZZZZZZZZ";
					--end if;
				when others =>
					RWflag <= '0';
					AD<="ZZZZZZZZ";
			end case;
	
	
			-- Latch data from Eth. Ctrl. on edge of count cycle 13 (1101)
			if rising_edge(fClk) then
				if count(3 downto 1)="110" and RiW_int='1' then 
					TxRx_Q <= AD;
				end if;
			end if;
			
	
			-- Latch the data that was passed in with "Go"
			if (falling_edge(fClk) and fGo='1') then
				RiW_int <= TxRx_RiW;
				Dout <= TxRx_D;
				Addr <= TxRx_A;
			else
				Addr <= Addr;
				Dout <= Dout;
				RiW_int <= RiW_int;		
			end if;
		end if;
	end process;
	
	-- raise flags approriate to request type
	iRD <= (not RiW_int) or RWflag;
	iWR <= RiW_int or RWflag;
	
end Behavioral;