----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    04:14:41 10/01/2007 
-- Design Name: 
-- Module Name:    MuxIntel - Behavioral 
-- Description:	   Module for communicating with the Ethernet Controller across
--		   the Multiplexed Intel bus. This module is also essential for  
--		   timing: specifies appropriate wait periods across the Intel 
-- 		   bus and subdivides the Clk used everywhere else on the FPGA.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity MuxIntel is
    Port ( fClk : in  STD_LOGIC; -- "fast" 20MHz clock
	   sClk : out STD_LOGIC; -- "slow"  5MHz clock
	   Rst : in STD_LOGIC;
	   -- MuxIntel lines ------------------------
	   ALE : out STD_LOGIC;
	   AD  : inout STD_LOGIC_VECTOR (7 downto 0);
	   iRD : out STD_LOGIC;
	   iWR : out STD_LOGIC;
	   -- FPGA-Internal input lines -------------
           Go  : in  STD_LOGIC;
           RiW : in  STD_LOGIC;
           A   : in  STD_LOGIC_VECTOR (7 downto 0);
           D   : in  STD_LOGIC_VECTOR (7 downto 0);

	   -- Output to internals -------------------
	   Q   : out STD_LOGIC_VECTOR (7 downto 0);
           Done : out  STD_LOGIC
	 );
end MuxIntel;

architecture Behavioral of MuxIntel is

	component pulser is
	    Port ( Clk : in  STD_LOGIC;
		   D   : in  STD_LOGIC;
           	   Q   : out  STD_LOGIC
		 );
	end component;

	component c_delay is
	    Port ( Clk : in  STD_LOGIC;
		   D   : in  STD_LOGIC;
           	   Q   : out  STD_LOGIC
		 );
	end component;

	component EdgeCounter4bit is
	    Port ( Clk : in  STD_LOGIC;
           	   Go : in  STD_LOGIC;
		   En : out STD_LOGIC;
           	   Q : out  STD_LOGIC_VECTOR (3 downto 0)
		 );
	end component;
	
	signal sClk_int : STD_LOGIC;
	signal TickCount : STD_LOGIC_VECTOR (1 downto 0);
	signal count : STD_LOGIC_VECTOR (3 downto 0);
	signal En_Convo : STD_LOGIC;
	signal Go_delayed : STD_LOGIC;
	
	signal Dout	: STD_LOGIC_VECTOR (7 downto 0);
	signal Addr	: STD_LOGIC_VECTOR (7 downto 0);
	signal RWflag  : STD_LOGIC;
	signal RiW_int : STD_LOGIC;
	signal fGo : STD_LOGIC;
	signal GObit : STD_LOGIC;

begin

	-- Clock subdivision (1/4th the frequency) ----------------
	sClk_int <= TickCount(1);
	sClk <= sClk_int;
	sCLKsubdiv : process (fClk,TickCount)
	begin
		if (Rst='1') then
			TickCount <= "00";
		else
			if (rising_edge(fClk)) then
				TickCount <= TickCount + "01";
			else
				TickCount <= TickCount;
			end if;
		end if;

	end process;
	-----------------------------------------------------------
	
	GObit <= '1' when Go='1' else '0';
	u1: pulser port map (fClk, GObit, fGo); -- Go signal trim
	
	-- Conversation process "metronome"
	u2: EdgeCounter4bit port map (fClk, fGo, En_Convo, count);
	
	-- "Done" on En's falling edge
	u3: c_delay port map (sClk_int, GObit, Go_delayed);
	u4: c_delay port map (sClk_int, Go_delayed, Done);
	
		
	-- Intel bus conversation schedule ------------------------------
	ConvoTiming : process (fClk, Rst, RiW_int, RiW, En_Convo, count, Addr, Dout)
	begin
		if (Rst='1') then
			RiW_int <= '0';
			ALE <= '0';
			Q <= X"00";
			AD <= "ZZZZZZZZ";
		else
			case count is -- | ALE flag | Data&Addr I/O | R/W flag assertions
				when "0000" =>
					ALE <= '1';
					AD <= X"00";
				  	RWflag <= '1'; 
				when "0001" =>
					AD <= Addr;
					RWflag <= RWflag;
				when "0011" =>
					ALE <= '0';
					RWflag <= RWflag;
				when "0101" =>
					AD<="ZZZZZZZZ";
					RWflag <= RWflag;
				when "0110" =>
					RWflag <= '0';
				when "1000" =>
					RWflag <= RWflag;
					if (RiW_int='0') then
						AD <= Dout;
					end if;
				when "1101" =>
					RWflag <= '1';
					if (RiW_int='1') then
						Q <= AD;
					end if;
				when "1111" =>
					RWflag <= RWflag;
					if (RiW_int='0') then
						AD <= "ZZZZZZZZ";
					end if;
				when others =>
					RWflag <= RWflag;   
			end case;
		
			-- Latch the data that was passed in with "Go"
			if (falling_edge(fClk) and fGo='1') then
				RiW_int <= RiW;
				Dout <= D;
				Addr <= A;
			else
				Addr <= Addr;
				Dout <= Dout;
				RiW_int <= RiW_int;		
			end if;
		end if;
	end process;
	
	-- raise flags approriate to request type
	iRD <= (not RiW_int) or RWflag;
	iWR <= RiW_int or RWflag;

end Behavioral;