----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    22:52:57 11/29/2007
-- Design Name: 
-- Module Name:    Reset_soft - Behavioral 
-- Description:    Loads the factory-coded MAC address from Flash memory into 
--		   MAC system registers.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity Reset_soft is
    Port ( Clk : in  STD_LOGIC;
	   Rst : in STD_LOGIC;
           DAC_iRST : out  STD_LOGIC;
           --ADC_Rst : out  STD_LOGIC;
			  
	   state_En : out STD_LOGIC;
	   state_D  : out STD_LOGIC_VECTOR (2 downto 0);
	   state_Q : in STD_LOGIC_VECTOR (2 downto 0);
			  
	   MACregs_En : out STD_LOGIC;
	   MACregs_A  : out STD_LOGIC_VECTOR (3 downto 0);
	   MACregs_D  : out STD_LOGIC_VECTOR (7 downto 0);

	   DBbyte	: out STD_LOGIC_VECTOR (7 downto 0);

	   --Transceiver control lines
	   TxRx_Go : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_RiW : out  STD_LOGIC;
	   TxRx_Q : in  STD_LOGIC_VECTOR (7 downto 0);
	   TxRx_Done : in  STD_LOGIC;
			  
	   ser_Go : out STD_LOGIC;
  	   ser_D : out STD_LOGIC_VECTOR (7 downto 0)
	 );
end Reset_soft;

architecture Behavioral of Reset_soft is
	
	signal ReadCount : STD_LOGIC_VECTOR (3 downto 0);
	signal Data, DBbyte_int : STD_LOGIC_VECTOR (7 downto 0);
	signal Go_Init, Go_Byte, Go, Go_late, Done_Byte, Done_Skip, Go_Skip, En : STD_LOGIC;
	signal TxRx_Go_uAutoRd, TxRx_Go_uPktSkip, MACrdStage, LastByte : STD_LOGIC;

begin

	-- Hold enable if state="001"
	En <= not (state_Q(2) or state_Q(1) or not state_Q(0));
	u1: Pulse_Delay port map (Clk, En, Go_Init);

	Go <= Go_Init or Done_Byte;
	--Go_Byte <= Go and not (ReadCount(3) and ReadCount(0));
	Go_Byte <= Go when LastByte='0' else '0';

	-- AUTORD through source address (reprinted in packet payload)
	uAutoRd: AutoRd
	port map (Clk, Rst, Go_Byte, Data, Done_Byte,
		  TxRx_Go_uAutoRd, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done);

	MACrdStage <= not (ReadCount(2) and ReadCount(1));
	LastByte <= Done_Byte when ReadCount(2 downto 0)="110" else '0';
	
	MACregs_En <= '1' when (Done_Byte and MACrdStage)='1' else '0';
	MACregs_A <= ReadCount when (Done_Byte and MACrdStage)='1' else "ZZZZ";
	MACregs_D <= Data when (Done_Byte and MACrdStage)='1' else "ZZZZZZZZ";

	ReadCount_ctrl : process (Rst, En, Go_Init, Done_Byte) begin
		if Rst='1' or Go_Init='1' then
			ReadCount <= "1111";
		else
			if rising_edge(Done_Byte) and En='1' then
				ReadCount <= ReadCount + "0001";
			else
				ReadCount <= ReadCount;
			end if;
		end if;
	end process;
	
	
--	debugbits : process (Rst,Done_Byte,ReadCount)  -- set timout multiple
--	begin
--		if (Rst='1') then
--			DBbyte_int <= "00000001";
--		else
--			if rising_edge(ReadCount(3)) then
--				DBbyte_int <= Data;
--			else
--				DBbyte_int <= DBbyte_int;
--			end if;
--		end if;
--	end process;
--	DBbyte <= DBbyte_int;
	
	
	DAC_iRst <= '0' when (Done_Byte='1' and Data(0)='1' and 
			ReadCount(2 downto 0)="110") else not Rst;

	-- Order RXSKIP (RXCN(1) - 0x11(1) ) of the packet
	Go_Skip <= LastByte;
	uPktSkip: wrToAddr
	port map (Clk, Rst, Go_Skip, X"11", "00000010",
		  TxRx_Go_uPktSkip, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_Skip);
	

	state_En <= Done_Skip;
	state_D <= "101" when (Done_Skip='1') else "ZZZ";

	TxRx_Go <= TxRx_Go_uAutoRd or TxRx_Go_uPktSkip;
	
	ser_Go <= Go_Byte;
	ser_D  <= X"0" & ReadCount when Done_Byte='1' else "ZZZZZZZZ";
end Behavioral;