----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    22:52:57 11/29/2007
-- Design Name: 
-- Module Name:    Reset_hard - Behavioral 
-- Description:   Performs cold reboot of the Ethernet Controller using its iRst 
--		  pin and conducts init. config.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity Reset_hard is
    Port ( Clk : in STD_LOGIC;
	   Rst : in STD_LOGIC;
	   Eth_iRst : inout STD_LOGIC;
			  
	   state_En : out STD_LOGIC;
	   state_D  : out STD_LOGIC_VECTOR (2 downto 0);
	   state_Q : in STD_LOGIC_VECTOR (2 downto 0);

	   MACregs_En : out STD_LOGIC;
	   MACregs_A  : out STD_LOGIC_VECTOR (3 downto 0);
	   MACregs_D  : out STD_LOGIC_VECTOR (7 downto 0);
			  
	   --Transceiver control lines
	   TxRx_Go : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_RiW : out  STD_LOGIC;
	   TxRx_Q : in  STD_LOGIC_VECTOR (7 downto 0);
	   TxRx_Done : in  STD_LOGIC;
			  
	   --Interrupt catcher control lines
	   INT_Go : out STD_LOGIC;
	   INT_Mask : out STD_LOGIC_VECTOR (7 downto 0);
	   INT_Found : in STD_LOGIC_VECTOR (7 downto 0);
	   INT_Done : in STD_LOGIC;

	   dbShort : in STD_LOGIC;
 	   ser_Go : out STD_LOGIC;
  	   ser_D : out STD_LOGIC_VECTOR (7 downto 0);

	   db1 : out STD_LOGIC;
	   db2 : out STD_LOGIC
	 );
end Reset_hard;

architecture Behavioral of Reset_hard is
	
	component MACaddrLoad is
	    Port ( Clk : in  STD_LOGIC;
		   Rst : in STD_LOGIC;
           	   Go : in  STD_LOGIC;
           	   Done : out  STD_LOGIC;

		   --MAC address register control lines
		   MACregs_En : out  STD_LOGIC;
		   MACregs_A  : out STD_LOGIC_VECTOR (3 downto 0);
		   MACregs_D  : out STD_LOGIC_VECTOR (7 downto 0);

		   --Transceiver control lines
		   TxRx_Go : out  STD_LOGIC;
           	   TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           	   TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
           	   TxRx_RiW : out  STD_LOGIC := 'Z';
		   TxRx_Q : in  STD_LOGIC_VECTOR (7 downto 0);
		   TxRx_Done : in  STD_LOGIC
		 );
	end component;
	
	component CleanTxBuf is
	    Port ( Clk : in  STD_LOGIC;
		   Rst : in STD_LOGIC;
           	   Go : in STD_LOGIC;
		   Done : out STD_LOGIC;
  
		   -- Transceiver control lines
		   TxRx_Go : out  STD_LOGIC;
           	   TxRx_RiW : out  STD_LOGIC;
           	   TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
		   TxRx_D : out STD_LOGIC_VECTOR (7 downto 0);
           	   TxRx_Done : in  STD_LOGIC;

		   -- Serial log output lines
 		   ser_Go : out STD_LOGIC;
  		   ser_D : out STD_LOGIC_VECTOR (7 downto 0);
		   db : out STD_LOGIC
		 );
	end component;


	signal WordCount : STD_LOGIC_VECTOR (1 downto 0);
	signal Data, MACCfg : STD_LOGIC_VECTOR (7 downto 0);
	signal MACCFin, IPGTin : STD_LOGIC_VECTOR (15 downto 0);
	signal MACregs_A_int : STD_LOGIC_VECTOR (3 downto 0);
	
	-- Separate Go lines for TxRx-talking modules to be ORed later
	signal TxRx_Go1, TxRx_Go11, TxRx_Go2, TxRx_Go12 : STD_LOGIC;
	signal TxRx_Go3, TxRx_Go13, TxRx_Go4, TxRx_Go14 : STD_LOGIC;
	signal TxRx_Go5, TxRx_Go15, TxRx_Go6, TxRx_Go16 : STD_LOGIC;
	signal TxRx_Go7, TxRx_Go17, TxRx_Go8, TxRx_Go18 : STD_LOGIC;
	signal TxRx_Go9, TxRx_Go19, TxRx_Go10, TxRx_Go20 : STD_LOGIC;
	signal TxRx_Go21 : STD_LOGIC; 

	signal Done_Wait1, Done_Wait2, Done_Wait2_nodb, Done_GetDuplex : STD_LOGIC;
	signal Done_MACCF, Done_MAC, Done_MACCF2, Done_MACCF3 : STD_LOGIC;
	signal Done_MACAddr, Done_MACconfig, Done_MAXLEN, Go_MACconfig : STD_LOGIC;
	
	signal Done_IPGT, Done_IPGR, Done_INT0en, Done_INT1en : STD_LOGIC;
	signal Done_LEDdis, Done_ResCfg, Done_EthiRST, Done_EthiRST_nodb : STD_LOGIC;

	signal Done_p0, Done_p1, Done_p2, Done_p3, Done_EnTxRx : STD_LOGIC;
	signal Done_p3_nodb, Done_SelfInit, Done_Filt, Go_SetRxFilt : STD_LOGIC;
	signal Done_Hash1, Done_Phy, Done_Hash2, Done_ResetHard, Done_AutoNeg : STD_LOGIC;
	signal Go_OnState, Go, Go_EthRst, Go_INT0en, Go_InitMAC : std_logic;
	signal EthRstHold, En, Go_SelfInitINT, AutoNegFailed, Go_InitPhy : STD_LOGIC;

	signal InitDelay : STD_LOGIC_VECTOR (1 downto 0);
	
	signal ser_Go_rc1 : STD_LOGIC;
begin

	ResetDB : process (Rst, Done_EthiRST_nodb)
	begin
		if Rst='1' then
			db1 <= '1';
		else
			if Done_Hash2='1' then
				db1 <= '0';
			end if;
		end if;
	end process;
	En <= not (state_Q(2) or state_Q(1) or state_Q(0));

	InitWait : process (Clk, Rst)
	begin
		if (Rst='1') then
			InitDelay <= "00";
		else
			if (rising_edge(Clk) and InitDelay(1)='0') then
				InitDelay <= InitDelay+"01";
			else
				InitDelay <= InitDelay;
			end if;
		end if;
	end process;

	--db2 <= Done_EthiRST;
	ser_Go <= Done_EthiRST or Done_MAC or ser_Go_rc1 or Go_MACconfig or
						(AutoNegFailed and Done_Phy);

	ser_D <= X"28" when Done_EthiRST='1' else  -- '('
		 X"29" when Done_MAC='1' else    -- ')'
		 X"2A" when Go_MACconfig='1' else
		 X"2B" when (AutoNegFailed and Done_Phy)='1' else   -- '+'
		"ZZZZZZZZ";
	
	g1: pulser port map (Clk, En, Go_OnState);  -- produce Go pulse on start of En
	Go <= InitDelay(0) or Go_OnState;

	--(1) Hold Eth's iRST pin low for 128 cycles > req. 15e-6 sec @ 5MHz CLK
	Go_EthRst <= Go and not dbShort;
	g2: Counter7bit port map (Clk, Rst, Go_EthRst, EthRstHold, Done_EthiRST_nodb);
	Eth_iRst <= '0' when ((EthRstHold or (dbShort and Go))='1') else 'Z';
   	Done_EthiRST <= Done_EthiRST_nodb or (Go and dbShort);

	
	g3: Trigger port map (Rst, Done_EthiRST, INT_Done, Go_SelfInitINT);
	g4: Trigger port map (Rst, Go_SelfInitINT, INT_Done, Done_SelfInit);
	INT_Go <= Done_EthiRST or Go_SelfInitINT or Done_EnTxRx;
	
	INT_Mask <= "11000000" when (Done_EthiRST or Go_SelfInitINT)='1' else "ZZZZZZZZ";

   ----------------------------------------------------------------------------
	--(4) DISABLE UNNECESSARY INTERRUPTS ---------------------------------------
	
	i1: wrToAddr
	port map (Clk, Rst, Done_SelfInit, X"64", "00110011",
		  TxRx_Go2, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_INT0en);

--	rc1: InspectReg
--	port map (Clk, Rst, Done_INT0, X"64", Go_INT0,
--		  TxRx_Go2b, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done, ser_Go_rc1, ser_D);
	Go_INT0en <= Done_INT0en;
	-- Disable all but "Auto-Neg. Failed" and "Auto-Neg. Complete" interrupts in INT1
	i2: wrToAddr
	port map (Clk, Rst, Go_INT0en, X"7D","00000101",
		  TxRx_Go3, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_INT1en);
	----------------------------------------------------------------------------


   ----------------------------------------------------------------------------
	--(5) INITIALIZATION OF THE PHYSICAL LAYER ---------------------------------

	Go_InitPhy <= Done_INT1en or AutoNegFailed;

	-- Disable PhyEN in PHYCN
	p0: wrToAddr
	port map (Clk, Rst, Go_InitPhy, X"78", "00000000",
		  TxRx_Go4, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_p0);
						
	-- Enable SMSQ, no LinkInteg., no JabberDetect, no AutoNeg, and AutoPolCorr., AdPause
	p1: wrToAddr
	port map (Clk, Rst, Done_p0, X"79", "11110110",
		  TxRx_Go5, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_p1);

	
	-- Disable transmitter powersave mode
	p2: wrToAddr
	port map (Clk, Rst, Done_p1, X"7A", "10000000",
		  TxRx_Go6, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_p2);

	-- Enable PhyEN in PHYCN (keep other settings)
	p3: wrToAddr
	port map (Clk, Rst, Done_p2, X"78", "10010000",
		  TxRx_Go7, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_p3);
	
	-- Wait 2*0.82ms (5MHz clock presumed. Typical initialization time: 1ms) ---
	Done_Wait2 <= '1' when ((dbShort and Done_p3)='1') else Done_Wait2_nodb;
	Done_p3_nodb <= Done_p3 when (dbShort='0') else '0';
	p4: Counter12bit port map (Clk, Rst, Done_p3_nodb,    Done_Wait1);
	p5: Counter12bit port map (Clk, Rst, Done_Wait1, Done_Wait2_nodb);

	-- Phy layer init complete -------------------------------------------------
		
	-- Enable Tx, Rx, (Full-Duplex bit ignored due to Auto-Neg.) in PHYCN
	p7: wrToAddr
	port map (Clk, Rst, Done_Wait2, X"78", "11110000",
		  TxRx_Go8, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_EnTxRx);

	p6: Trigger port map (Rst, Done_EnTxRx, INT_Done, Done_AutoNeg);
	INT_Mask <= "00001010" when Done_EnTxRx='1' else "ZZZZZZZZ";
	AutoNegFailed <= Done_AutoNeg and INT_Found(3);
	Done_Phy <= Done_AutoNeg and INT_Found(1) and not INT_Found(3);
	----------------------------------------------------------------------------

   ----------------------------------------------------------------------------
	--(6) DISABLE LEDS AND UNNECESSARY RESET SOURCES  --------------------------

	-- Disable software reset and Vdd (power failure detection reset)
	p9: wrToAddr
	port map (Clk, Rst, Done_Phy, X"72", "00000000",
		  TxRx_Go10, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_ResCfg);

	--p11: c_delay port map (Clk, Done_ResCfg, Go_InitMAC);

	-- Disable LEDs but keep internal weak pull-ups (0x70(1)=0) enabled
	p10: wrToAddr
	port map (Clk, Rst, Done_ResCfg, X"70", "00001100",
		  TxRx_Go11, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_LEDdis);
	----------------------------------------------------------------------------

   ----------------------------------------------------------------------------
	--(7) INITIALIZATION OF THE MEDIA ACCESS CONTROLLER (MAC) ------------------


	-- Determine whether the physical layer is in half or full duplex
	m0: getByte
	port map (Clk, Rst, Done_LEDdis, X"78", Data, Done_GetDuplex,
		  TxRx_Go12, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done);

	-- reg. to remember data from m0 and delay next step till data is latched
	m1a: Reg8bit port map (Clk, Rst, Done_GetDuplex, Data, MACCfg);
	m1b: c_delay port map (Clk, Done_GetDuplex, Go_MACconfig);
	
	-- Write 0x40B3 (full-duplex) or 0x4012 (half-duplex) to MACCF
	--   MACCfg(4) carries duplex info (Full='1')
	MACCFin <= 	X"40" & MACCfg(4) & '0' & MACCfg(4) & "1001" & MACCfg(4);
	m2: MACwrToAddr
	port map (Clk, Rst, Go_MACconfig, X"01", MACCFin,
		  TxRx_Go13, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_MACCF);
						
	-- Write 0x0015 (full-duplex) or 0x0012 (half-duplex) to IPGT
	IPGTin <= X"00" & "00010" & MACCfg(4) & (not MACCfg(4)) & MACCfg(4);
	--IPGTin <= X"0015";
	m3: MACwrToAddr
	port map (Clk, Rst, Done_MACCF, X"02", IPGTin,
		  TxRx_Go14, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_IPGT);

	-- Configure IPGR to manual's recommendation
	m4: MACwrToAddr
	port map (Clk, Rst, Done_IPGT, X"03", X"0C12",
		  TxRx_Go15, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_IPGR);

--	-- Configure MAXLEN to manual's recommendation
--	m5: MACwrToAddr port map (Clk, Rst, Done_IPGR, X"05", X"05EE",
--						TxRx_Go16, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_MAXLEN);
	Done_MAXLEN <= Done_IPGR;

	-- Load MAC address from flash memory
	m6: MACaddrLoad
	port map (Clk, Rst, Done_MAXLEN, Done_MACaddr,
		  MACregs_En, MACregs_A_int, MACregs_D,
		  TxRx_Go17, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Q, TxRx_Done);                
	MACregs_A <= MACregs_A_int when state_Q="000" else "ZZZZ";

	-- Start enable reception 
	m7: MACwrToAddr
	port map (Clk, Rst, Done_MACaddr, X"00", X"000" & "1001",
		  TxRx_Go18, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_MAC);

	----------------------------------------------------------------------------

--	c1: CleanTxBuf port map (Clk, Rst, Done_MAC, Go_SetRxFilt,
--						TxRx_Go_c1, TxRx_RiW, TxRx_A, TxRx_D, TxRx_Done);
	Go_SetRxFilt <= Done_MAC;

	--(8) Configure RXFILT (0x10) to accept broad- and multi-cast packets but no runts
	f1: wrToAddr
	port map (Clk, Rst, Go_SetRxFilt, X"10", "00001000",
		  TxRx_Go19, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_Filt);
	
	-- Configure the hash table to accept all packets
	f2: wrToAddr
	port map (Clk, Rst, Done_Filt, X"0E", X"FF",
		  TxRx_Go20, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_Hash1);
	f3: wrToAddr
	port map (Clk, Rst, Done_Hash1, X"0F", X"FF",
		  TxRx_Go21, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_Hash2);

	--f4: Counter16bit port map (Clk, Rst, Done_Hash2, Done_ResetHard);
	Done_ResetHard <= Done_Hash2;

	-- put FPGA in Status packet transmit mode 
	state_En <= Done_ResetHard;
	--state_D <= "101" when (Done_Hash2='1') else "ZZZ";  
	state_D <= "100" when (Done_ResetHard='1') else "ZZZ";  --Launch Querier
	--state_D <= "001" when (Done_ResetHard='1') else "ZZZ";  

	TxRx_Go <= En and (TxRx_Go1 or TxRx_Go2 or TxRx_Go3 or TxRx_Go4 or
			   TxRx_Go5 or TxRx_Go6 or TxRx_Go7 or TxRx_Go8 or
			   TxRx_Go9 or TxRx_Go10 or TxRx_Go11 or TxRx_Go12 or
			   TxRx_Go13 or TxRx_Go14 or TxRx_Go15 or TxRx_Go16 or
			   TxRx_Go17 or TxRx_Go18 or TxRx_Go19 or TxRx_Go20 or TxRx_Go21);
				  
end Behavioral;