----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    22:52:57 11/29/2007
-- Design Name: 
-- Module Name:    MACaddrLoad - Behavioral 
-- Description:   Loads the factory-coded MAC address from Flash memory into 
--		  MAC system registers.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;


entity MACaddrLoad is
    Port ( Clk : in  STD_LOGIC;
	   Rst : in STD_LOGIC;
           Go : in  STD_LOGIC;
           Done : out  STD_LOGIC;
			  
	   --MAC address register control lines
	   MACregs_En : out  STD_LOGIC;
	   MACregs_A  : out STD_LOGIC_VECTOR (3 downto 0);
	   MACregs_D  : out STD_LOGIC_VECTOR (7 downto 0);
			  
	   --Transceiver control lines
	   TxRx_Go : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_RiW : out  STD_LOGIC;
	   TxRx_Q : in  STD_LOGIC_VECTOR (7 downto 0);
	   TxRx_Done : in  STD_LOGIC);
end MACaddrLoad;

architecture Behavioral of MACaddrLoad is
	
	component MACwrToAddr is
	    Port ( Clk : in  STD_LOGIC;
		   Rst : STD_LOGIC;
		   Go : in STD_LOGIC;                      -- pulse to start
		   A : in STD_LOGIC_VECTOR (7 downto 0);   -- address
		   D : in STD_LOGIC_VECTOR (15 downto 0);  -- data to be written
           	   -- Transceiver control lines
		    TxRx_Go : out  STD_LOGIC;
           	   TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           	   TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
           	   TxRx_RiW : out  STD_LOGIC;
		   TxRx_Done : in  STD_LOGIC;

		   Done : out STD_LOGIC
		 );
	end component;

	component Reg8bit is
	    Port ( Clk : in  STD_LOGIC;
           	   Rst : in  STD_LOGIC;
           	   En : in  STD_LOGIC;
           	   D : in  STD_LOGIC_VECTOR (7 downto 0);
           	   Q : out  STD_LOGIC_VECTOR (7 downto 0)
		 );
	end component;

	signal En : STD_LOGIC;
	signal Done_int : STD_LOGIC;
	--signal WordCount : STD_LOGIC_VECTOR (1 downto 0);
	signal iWordCount : STD_LOGIC_VECTOR (1 downto 0);
	signal MACbytenum : STD_LOGIC_VECTOR (3 downto 0);
	signal Data : STD_LOGIC_VECTOR (7 downto 0);
	signal Go_Byte1 : STD_LOGIC;
	signal Go_Byte2 : STD_LOGIC;
	signal Done_Byte2 : STD_LOGIC;
	--signal Done_SetMACAddr : STD_LOGIC;
	signal FinalMACword : STD_LOGIC;
	signal Done_Word : STD_LOGIC;
	signal Done_Byte1 : STD_LOGIC;
	signal Done_Byte_late : STD_LOGIC;
	signal Done_FlashAddr : STD_LOGIC;

	signal MACword : STD_LOGIC_VECTOR (15 downto 0);
	signal IndirMACaddr : STD_LOGIC_VECTOR (7 downto 0);

	signal TxRx_Go1 : STD_LOGIC;
	signal TxRx_Go2 : STD_LOGIC;
	signal TxRx_Go3 : STD_LOGIC;
	signal TxRx_Go4 : STD_LOGIC;

begin

	-- Set Flash memory pointer (FLASHADDRH(0x69):FLASHADDRL(0x68)) to the 
	-- beginning of factory-stored MAC address. Note that the pointer regs. are 
	-- numbered in reverse order so LSByte (FA) is given first, hence the 
	-- 16bit flash mem. address is bytewise reversed (e.g. FA1F instead of 1FFA)
	a1: wr2BtoAddr
	port map (Clk, Rst, Go, X"68", X"FA1F", 
		  TxRx_Go1, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_FlashAddr);
	
	FinalMACword <= iWordCount(1) xor iWordCount(0);

	Go_Byte1 <= Done_FlashAddr or (Done_Word and En);

	--Done_int <= Done_Word and not WordCount(1) and not WordCount(0);
	Done_int <= Done_Word and FinalMACword;
	
	--Done <= Done_int;
	u1: c_delay port map (Clk, Done_int, Done);
	
	-- Use FlashAutoRD interface to scroll through the 6 bytes of the MAC addr.
	-- 2 bytes at a time, storing in 16bit reg.
	
	-- MSByte:
	b1: getByte
	port map (Clk, Rst, Go_Byte1, X"05", Data, Done_Byte1,
		  TxRx_Go2, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done);
	-- now hold received MSByte in a register
	b1reg: Reg8bit port map (Clk, Rst, Done_Byte1, Data, MACword(15 downto 8)); 
	
	u2: c_delay port map (Clk, Done_Byte1, Go_Byte2);
	
	-- LSByte:
	b2: getByte
	port map (Clk, Rst, Go_Byte2, X"05", Data, Done_Byte2,
		  TxRx_Go3, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done);
	-- now hold received LSByte in a register
	b2reg: Reg8bit port map (Clk, Rst, Done_Byte2, Data, MACword(7 downto 0));


	MACregs_En <= Done_Byte1 or Done_Byte2;
	--MACregs_A <= (iWordCount(1) nand iWordCount(0)) & iWordCount
	--		 & Done_Byte2 when (En and (Done_Byte1 or Done_Byte2))='1' else "ZZZZ";
	MACregs_A <= MACbytenum when (Done_Byte1 or Done_Byte2)='1' else "ZZZZ";
	MACregs_D <= Data when (Done_Byte1 or Done_Byte2)='1' else "ZZZZZZZZ";
	

	-----------------------------------------------------------------------------------
	-- Set MACADDR to the proper indirect 16-bit register LSB-numbered: WordCount
	IndirMACaddr <= "000100" & iWordCount(1) & not iWordCount(0);
	
	m: MACwrToAddr
	port map (Clk, Rst, Done_Byte2, IndirMACaddr, MACword,
		  TxRx_Go4, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_Word);

	-----------------------------------------------------------------------------------
	TxRx_Go <= TxRx_Go1 or TxRx_Go2 or TxRx_Go3 or TxRx_Go4;
	
	MACbytenum(0) <= Done_Byte2;
	MACbyteCount : process (Rst,Go, Done_Word, Rst, En, Done_int)
	begin
		if (Go='1') then
--			WordCount <= "10";
--			iWordCount <= "00";
			iWordCount <= "11";
			MACbytenum(3 downto 1) <= "011";
		else
			if falling_edge(Clk) and Done_Word='1' and FinalMACword='0' then
				--WordCount <= WordCount - "01";
				iWordCount <= iWordCount + "01";
				MACbytenum(3 downto 1) <= MACbytenum(3 downto 1) + "001";
			else
				--WordCount <= WordCount;
				iWordCount <= iWordCount;
				MACbytenum(3 downto 1) <= MACbytenum(3 downto 1);
			end if;
			
		end if;
		
		if Rst='1' then
			En <= '0';
		else
			if Go='1' then
				En <= '1';
			else
				if falling_edge(Clk) and Done_Byte2='1' and FinalMACword='1' then 
					En <= '0';
				else
					En <= En;
				end if;
			end if;
		end if;
	end process;

end Behavioral;