--------	--------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    09:34:21 09/24/2007 
-- Design Name: 	 State Register
-- Module Name:    statereg - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 3 bit register for storing the state of the FPGA core
--						according to which module should be active.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity stateReg is
    Port ( Clk : in  STD_LOGIC;
			  Rst : in  STD_LOGIC;
           En : in  STD_LOGIC;
           D : in  STD_LOGIC_VECTOR (2 downto 0);
           Q : out  STD_LOGIC_VECTOR (2 downto 0));
end stateReg;

architecture Behavioral of stateReg is

	signal state : STD_LOGIC_VECTOR (2 downto 0);

begin
	
	statereg : process (Clk, Rst, En)
	begin
		if (Rst = '1') then
			state <= "000";
		else
			if (falling_edge(Clk) and En='1') then
				state <= D;
			else
				state <= state;
			end if;
			
			if rising_edge(Clk) 
				then Q <= state; 
			end if;
			
		end if;
	end process statereg;

	--Q <= state;
	
end Behavioral;