----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    10:13:13 09/24/2007 
-- Design Name: 	 Temperature Register
-- Module Name:    TempReg - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 	 10-bit register to store the temperature reported by the
--							Temperature sensor. Output is zero-padded 16bit.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TempReg is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Wr : in  STD_LOGIC;
           D : in  STD_LOGIC_VECTOR (9 downto 0);
           Q : out  STD_LOGIC_VECTOR (15 downto 0));
end TempReg;

architecture Behavioral of TempReg is

	signal Temp : STD_LOGIC_VECTOR (9 downto 0);

begin

	TempReg : process (Clk, Rst, Wr, D)
	begin
		if (Rst = '1') then
			Temp <= "0000000000";
		else
			if falling_edge(Clk) then
				if (Wr = '1') then
					Temp <= D;
				else
					Temp <= Temp;
				end if;
			else
				Temp <= Temp;
			end if;
		end if;
	end process TempReg;

	Q <= "000000" & Temp;

end Behavioral;