----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    10:22:32 09/24/2007 
-- Design Name:    Multiplexed Registers for DAC voltage values
-- Module Name:    MACregs - Behavioral 
-- Description: 	 12 x 8bit muxed register bank for storage of 2 MAC addresses.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MACregs is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Wr : in  STD_LOGIC;
           Addr : in  STD_LOGIC_VECTOR (3 downto 0);
           D : in  STD_LOGIC_VECTOR (7 downto 0);
           Q : out  STD_LOGIC_VECTOR (7 downto 0));
end MACregs;

architecture Behavioral of MACregs is
	
	type registers16bit is array (integer range <>) of STD_LOGIC_VECTOR (7 downto 0);
	signal reg : registers16bit (11 downto 0);
	signal intAddr :  integer range 11 downto 0;
	signal AddrChecked : STD_LOGIC_VECTOR (3 downto 0);


begin

	intAddr <= conv_integer(AddrChecked);

	MACregs : process (Clk, Rst, Wr, D, intAddr, Addr)
	begin
		for i in 3 downto 0 loop
			if (Addr(i)/='Z') then 	AddrChecked(i) <= Addr(i);
			else 							AddrChecked(i) <='0'; end if;
		end loop;
	
		if (Rst = '1') then
			for i in 11 downto 0 loop
				reg(i) <= X"FF";
			end loop;
		else
			if falling_edge(Clk) then
				if (Wr = '1') then
					reg(intAddr) <= D;
				else
					reg <= reg;
				end if;
			else
				reg <= reg;
			end if;
		end if;
	end process MACregs;

	Q <= reg(intAddr);

end Behavioral;