----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    10:22:32 09/24/2007 
-- Design Name:    Multiplexed Registers for DAC voltage values
-- Module Name:    DACregs - Behavioral 
-- Description: 	 32 x 14bit muxed register bank with 16bit (0-padded) output
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DACregs is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Wr : in  STD_LOGIC;
           Addr : in  STD_LOGIC_VECTOR (4 downto 0);
           D : in  STD_LOGIC_VECTOR (13 downto 0);
           Q : out  STD_LOGIC_VECTOR (15 downto 0));
end DACregs;



architecture Behavioral of DACregs is
	

	component Reg32x14bit_wPrim is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Wr : in  STD_LOGIC;
           Addri : in  STD_LOGIC_VECTOR (4 downto 0);
           Addro : in  STD_LOGIC_VECTOR (4 downto 0);
           D : in  STD_LOGIC_VECTOR (13 downto 0);
           Q : out  STD_LOGIC_VECTOR (13 downto 0));
	end component;

	signal Q_int : STD_LOGIC_VECTOR (13 downto 0);
begin

	u1: Reg32x14bit_wPrim port map (Clk, Rst, Wr, 
           Addr, Addr, D, Q_int);

	Q <= "00" & Q_int;
end Behavioral;







--architecture Behavioral of DACregs is
--	
--	type registers12bit is array (integer range <>) of STD_LOGIC_VECTOR (13 downto 0);
--	signal reg : registers12bit (31 downto 0);
--	signal intAddr :  integer range 31 downto 0;
--
--begin
--
--	intAddr <= conv_integer(Addr);
--
--	DACregs : process (Clk, Rst, Wr, D, intAddr, Addr)
--	begin
--	
--		if (Rst = '1') then
--			for i in 31 downto 0 loop
--				reg(i) <= "00000000000000";
--			end loop;
--		else
--			if falling_edge(Clk) then
--				if (Wr = '1') then
--					reg(intAddr) <= D;
--				else
--					reg <= reg;
--				end if;
--			else
--				reg <= reg;
--			end if;
--		end if;
--	end process DACregs;
--
--	Q <= "00" & reg(intAddr);
--
--end Behavioral;