----------------------------------------------------------------------------------
-- Company:  University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    10:22:32 09/24/2007 
-- Design Name:    Multiplexed Registers to store ADC-measured values
-- Module Name:    ADCregs - Behavioral 
-- Description: 	 8 x 12bit muxed register bank with 16bit (0-padded) output
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ADCregs is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Wr : in  STD_LOGIC;
           Addr : in  STD_LOGIC_VECTOR (2 downto 0);
           D : in  STD_LOGIC_VECTOR (11 downto 0);
           Q : out  STD_LOGIC_VECTOR (15 downto 0));
end ADCregs;

architecture Behavioral of ADCregs is
	
	type registers12bit is array (integer range <>) of STD_LOGIC_VECTOR (11 downto 0);
	signal reg : registers12bit (7 downto 0);
	signal intAddr :  integer range 7 downto 0;
begin

	intAddr <= conv_integer(Addr);

	ADCregs : process (Clk, Rst, Wr, D, intAddr,Addr)
	begin
	
		if (Rst = '1') then
			for i in 7 downto 0 loop
				reg(i) <= "000000000000";
			end loop;
--			reg(0) <= "000000000001";
--			reg(1) <= "000000000010";
--			reg(2) <= "000000000011";
--			reg(3) <= "000000000100";
--			reg(4) <= "000000000101";
--			reg(5) <= "000000000110";
--			reg(6) <= "000000000111";
--			reg(7) <= "000000001000";

		else
			if falling_edge(Clk) then
				if (Wr = '1') then
					reg(intAddr) <= D;
				else
					reg <= reg;
				end if;
			else
				reg <= reg;
			end if;
		end if;
	end process ADCregs;

	Q <= "0000" & reg(intAddr);

end Behavioral;