----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    04:14:41 10/01/2007 
-- Design Name: 
-- Module Name:    Reader_ctrl - Behavioral 
-- Dependencies:   Runs through the packet header and first two bytes to either
--			1. Discard packet not meant for this address
--			2. Switch to Query, Transmit or Reset
--			See below for acceptable packets properties
--
--
-- Packet relevant to this board: 1st payload byte == LocStamp 
--                                            [or] == 0xFF   <- custom multicast
-- PC->FPGA Packet Type requirements:
----------------------------------------------------
---| 	Type   	      |	Hex | 	   Bin 	  |  State 
----------------------------------------------------
---|	 P		0x50   	0101 0000    110
---|	 Q		0x51	0101 0001    100
---|	 R		0x52	0101 0010    000
---|	"R'"		0xD2	1101 0010    001
----------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity Reader is
    Port ( Clk : in  STD_LOGIC;
	   Rst : in STD_LOGIC;

           state_En : out  STD_LOGIC;
           state_D : out  STD_LOGIC_VECTOR (2 downto 0);
           state_Q : in  STD_LOGIC_VECTOR (2 downto 0);

	   LocStamp : in STD_LOGIC_VECTOR (7 downto 0);

	   --Transceiver control lines
	   TxRx_Go : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_RiW : out  STD_LOGIC;
	   TxRx_Q : in  STD_LOGIC_VECTOR (7 downto 0);
	   TxRx_Done : in  STD_LOGIC;
			  
 	   ser_Go : out STD_LOGIC;
  	   ser_D : out STD_LOGIC_VECTOR (7 downto 0);
	   db : out STD_LOGIC
	 );
end Reader;

architecture Behavioral of Reader is
	
	signal Data : STD_LOGIC_VECTOR (7 downto 0);

	signal InitGo : STD_LOGIC;
	signal En : STD_LOGIC;
	signal En_onClk : STD_LOGIC;
	
	signal Go_ReadByte : STD_LOGIC;
	signal Done_Cyc14 : STD_LOGIC;
	signal Done_ByteRead : STD_LOGIC;
	--signal Count_step : STD_LOGIC;
	signal Go_NextByte : STD_LOGIC;

	--signal Done_2ndByte : STD_LOGIC;
	signal Discard : STD_LOGIC;
	--signal chkDiscard : STD_LOGIC;
	--signal Done_Switch : STD_LOGIC;
	signal TxRx_Go_s2 : STD_LOGIC;
	signal TxRx_Go_d : STD_LOGIC;
	signal Done : STD_LOGIC;
	signal newstate : STD_LOGIC_VECTOR (2 downto 0);
	signal count : STD_LOGIC_VECTOR (3 downto 0);

begin

	En <= not state_Q(2) and state_Q(1) and state_Q(0);
	-- Define InitGo
	u1: c_delay port map (Clk, En, En_onClk);
	u2: pulser port map (Clk, En_onClk, InitGo); 	

	-- shift through 14 initial bytes of the packet via AUTORD interface
	CountSteps : process (InitGo,Go_NextByte)--Clk,Count_step)
	begin
		if (InitGo='1') then
			count <= "0000";
		else
			if falling_edge(Go_NextByte) then
				count <= count + "0001";
			else
				count <= count;
			end if;
		end if;
	end process;
	
	Go_ReadByte <= '1' when ((Go_NextByte or InitGo)='1') else '0';

	MonitorBytes : process (Done_ByteRead)
	begin
		if (Done_ByteRead='1') then
			if (count="1110") then 		-- 14(+1)th byte: 1st payload char: examine location stamp
				if (Data=LocStamp or Data=X"FF") then
					Discard <= '0';	newstate <= "011";
					Go_NextByte <= '1';
				else
					Discard <= '1';	newstate <= "010";
					Go_NextByte <= '0';
				end if;
			elsif (count="1111") then		-- 15(+1)th byte: 2nd payload char: packet type
				Go_NextByte <= '0';
				if (Data(6 downto 2)="10100") then
					case Data(1 downto 0) is
						when "10" =>
							newstate(2 downto 1) <= "00"; -- if "R" (reset)
							Discard <= not Data(7);
						when "01" => 
							newstate(2 downto 1) <= "10"; -- if "Q" (query)
							Discard <= '1';
						when "00" =>
							newstate(2 downto 1) <= "11"; -- if "P" (program DAC)
							Discard <= '0';
						when others =>
							newstate(2 downto 1) <="01"; -- other (e.g. S from others)
							Discard  <= '1';
					end case;
					-- allow soft reset (001) based on Data's MSB if 0&Data(6->0) spell R
					newstate(0) <= Data(7) and (Data(1) and not Data(0));
				else
					Discard  <= '1';
					newstate <= "010";
				end if;
	
			else
				Discard <= '0';
				newstate <= "011";
				Go_NextByte <= '1';
			end if;
		else
			Discard <= '0';
			newstate <= "011";
			Go_NextByte <= '0';
		end if;

	end process;
	
	ser_Go <= '1' when (Done_ByteRead='1' and count="1111") else '0';
	ser_D <= Data when (Done_ByteRead='1' and count="1111") else "ZZZZZZZZ";
	
	s2: AutoRd
	port map (Clk, Rst, Go_ReadByte, Data, Done_ByteRead, 
		  TxRx_Go_s2, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done);
	--Done_ByteRead <= Go_ReadByte;

	d: wrToAddr
	port map (Clk,Rst,Discard, X"11","00000010",
		  TxRx_Go_d,TxRx_A,TxRx_D,TxRx_RiW,TxRx_Done);

	Done <= '1' when (count="1111" and Done_ByteRead='1') else 'Z';

	state_En <= Done;
	state_D  <= newstate when (Done='1') else "ZZZ";
	
	TxRx_Go <= TxRx_Go_d or TxRx_Go_s2;

end Behavioral;