----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    04:14:41 10/01/2007 
-- Design Name: 
-- Module Name:    Reader_ctrl - Behavioral 
-- Dependencies:   Runs through the packet header and first two bytes to either
--			1. Discard packet not meant for this address
--			2. Switch to Query, Transmit or Reset
--			See below for acceptable packets properties
--
--
-- Packet relevant to this board: 1st payload byte == LocStamp 
--                                            [or] == 0xFF   <- custom multicast
-- PC->FPGA Packet Type requirements:
-------------------------------------------------------------
---| Type | Hex |		Bin    |  State || Pkt.Fate
-------------------------------------------------------------
---|	 P		0x50	 0101 0000    110      keep
---|	 Q		0x51	 0101 0001    100     discard
---|	 R		0x52	 0101 0010    000     discard
---|	"R'"		0xD2	 1101 0010    001      keep
-------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity Reader is
    Port ( Clk : in  STD_LOGIC;
	   Rst : in STD_LOGIC;

           state_En : out  STD_LOGIC;
           state_D : out  STD_LOGIC_VECTOR (2 downto 0);
           state_Q : in  STD_LOGIC_VECTOR (2 downto 0);

	   LocStamp : in STD_LOGIC_VECTOR (7 downto 0);

	   --Transceiver control lines
	   TxRx_Go : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_RiW : out  STD_LOGIC;
	   TxRx_Q : in  STD_LOGIC_VECTOR (7 downto 0);
	   TxRx_Done : in  STD_LOGIC;
			  
 	   ser_Go : out STD_LOGIC;
  	   ser_D : out STD_LOGIC_VECTOR (7 downto 0);
	   db : out STD_LOGIC
	 );
end Reader;

architecture Behavioral of Reader is
	
	signal newstate : STD_LOGIC_VECTOR (2 downto 0);
	signal count : STD_LOGIC_VECTOR (3 downto 0);
	signal Data : STD_LOGIC_VECTOR (7 downto 0);
	signal InitGo, En, Go_ReadByte, Go_NextByte, Go_Discard : STD_LOGIC;
	signal PermitNextByte, Discard, Done_ByteRead, Done, Done_proc : STD_LOGIC;
	signal TxRx_Go_s2, TxRx_Go_d : STD_LOGIC;

begin

	En <= not state_Q(2) and state_Q(1) and state_Q(0);
	-- Define InitGo
	u1: Pulse_Delay port map (Clk, En, InitGo); 	

	-- shift through 14 initial bytes of the packet via AUTORD interface
	CountSteps : process (InitGo,Go_NextByte,Clk)
	begin
		if (Rst='1' or InitGo='1') then
			count <= "0000";
		else
			if falling_edge(Clk) and (Go_NextByte and PermitNextByte)='1' then
				count <= count + "0001";
			else
				count <= count;
			end if;
		end if;
	end process;
	
	u3: c_delay port map (Clk, Done_ByteRead, Go_NextByte);
	--u3: Counter16bit port map (Clk, Rst, Done_ByteRead, Go_NextByte);

	Go_ReadByte <= (Go_NextByte or InitGo) and PermitNextByte;
	Done_proc <= Go_NextByte when count="1111" else '0';
	Go_Discard <= Done_proc and Discard;

	s2: AutoRd
	port map (Clk, Rst, Go_ReadByte, Data, Done_ByteRead, 
		  TxRx_Go_s2, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done);

	d: wrToAddr
	port map (Clk, Rst, Go_Discard, X"11","00000010",
		  TxRx_Go_d,TxRx_A,TxRx_D,TxRx_RiW,TxRx_Done);

	MonitorBytes : process (Rst,Done_ByteRead)
	begin
		if (Rst='1' or InitGo='1') then
			PermitNextByte <= '1'; Discard <= '0';
		else
			if (falling_edge(Clk) and Done_ByteRead='1') then
				if (count="1110") then 		-- 14(+1)th byte: 1st payload char: examine location stamp
					PermitNextByte <= '1'; 
					if (Data=LocStamp or Data=X"FF") then
						--PermitNextByte <= '1'; 
						Discard <= '0';	
					else
						--PermitNextByte <= '0'; 
						Discard <= '1';
						newstate <= "010";
					end if;
				elsif (count="1111") then	-- 15(+1)th byte: 2nd payload char: packet type
					PermitNextByte <= '0';
					if Discard='0' then -- i.e. not sure if to discard packet yet?
						if (Data(6 downto 2)="10100") then
							case Data(1 downto 0) is
								when "10" => 
									newstate(2 downto 1) <= "00"; -- if "R" (reset)
									Discard <= not Data(7);
								when "01" =>
									newstate(2 downto 1) <= "10"; -- if "Q" (query)
									Discard <= '1';
								when "00" =>
									newstate(2 downto 1) <= "11"; -- if "P" (program DAC)
									Discard <= '0';
								when others =>
									newstate(2 downto 1) <="01";-- other (e.g. S from others)
									Discard  <= '1';
							end case;
							-- allow soft reset (001) based on Data's MSB if 0&Data(6->0) spell R
							newstate(0) <= Data(7) and (Data(1) and not Data(0));
						else
							Discard  <= '1';
							newstate <= "010";
						end if;
					end if;
				else
					Discard <= '0';	
					PermitNextByte <= '1';
				end if;
			else
				Discard <= Discard;
				PermitNextByte <= PermitNextByte;
			end if;
		end if;
	end process;
	
	--ser_Go <= Done_ByteRead when count(3 downto 2)="11" else '0';
	--ser_D <= "0000" & count when (Done_ByteRead='1' and count(3 downto 2)="11") else "ZZZZZZZZ";
	ser_Go <= Go_Discard;
	ser_D <= X"40" when Go_Discard='1' else "ZZZZZZZZ";
	
	--u4: Counter16bit port map (Clk, Rst, Done_proc, Done);
	u4: c_dbldelay port map (Clk, Done_proc, Done);
	--Done <= '1' when (count="1111" and Done_ByteRead='1') else '0';

	state_En <= Done;
	state_D  <= newstate when (Done='1') else "ZZZ";
	--state_D  <= "100" when (Done='1') else "ZZZ";

	TxRx_Go <= TxRx_Go_d or TxRx_Go_s2;

end Behavioral;