----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    14:48:00 09/24/2007 
-- Design Name: 
-- Module Name:    Querier_coord - Behavioral 
-- Description:    Queriers the ADC and Temperature sensor 
--		   Sets state 101 (Transmit "S") upon completion

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

Entity Querier is
    Port ( Clk : in STD_LOGIC;
	   Rst : in  STD_LOGIC;

	   -- SPI bus (with ADC and Temp sensors) lines
	   SPI_SCLK : out STD_LOGIC;
	   SPI_T_CE : out STD_LOGIC;
	   SPI_A_iCS : out STD_LOGIC;
	   SPI_SDI : out STD_LOGIC;
	   SPI_SDO : in STD_LOGIC;

	   -- Registers
	   ADCreg_En : out  STD_LOGIC;
	   ADCreg_A  : out STD_LOGIC_VECTOR (2 downto 0);
	   ADCreg_D  : out STD_LOGIC_VECTOR (11 downto 0);
	   Tempreg_En : out STD_LOGIC;
	   Tempreg_D : out  STD_LOGIC_VECTOR (9 downto 0);

	   -- state bus
	   stateEn : out STD_LOGIC;
	   stateD : out  STD_LOGIC_VECTOR (2 downto 0);
	   stateQ : in STD_LOGIC_VECTOR (2 downto 0);		

	   ser_Go : out STD_LOGIC;
	   ser_D : out STD_LOGIC_VECTOR (7 downto 0);
	   db : out STD_LOGIC
	 );
end Querier;


architecture Behavioral of Querier is

	component GetTempVal is
	    Port ( Clk : in  STD_LOGIC;
          	   Rst : in  STD_LOGIC;
           	   Go : in  STD_LOGIC;
           	   Q : out  STD_LOGIC_VECTOR (9 downto 0);
           	   Done : out  STD_LOGIC;

		   --SPI bus
           	   T_CE : out  STD_LOGIC;
           	   SDO   : in  STD_LOGIC;

		   ser_Go : out STD_LOGIC;
		   ser_D : out STD_LOGIC_VECTOR (7 downto 0);
		   db : out STD_LOGIC
		 );
	end component;

	component GetADCval is
	    Port ( Clk : in  STD_LOGIC;
        	   Rst : in  STD_LOGIC;
        	   Go : in  STD_LOGIC;
        	   Addr : in  STD_LOGIC_VECTOR (2 downto 0);
        	   Q : out  STD_LOGIC_VECTOR (11 downto 0);
        	   Done : out  STD_LOGIC;

		   --SPI bus
           	   A_iCS : out  STD_LOGIC;
           	   SDI : out  STD_LOGIC;
           	   SDO : in  STD_LOGIC;
			  
		   ser_Go : out STD_LOGIC;
  		   ser_D : out STD_LOGIC_VECTOR (7 downto 0);
		   db : out STD_LOGIC
		 );
	end component;

	signal En, InitGo, Go_ADC, Done_query : STD_LOGIC;
	signal Done_ADC, Done_Temp, Done_ADC_delayed : STD_LOGIC;
	signal ChanCnt : STD_LOGIC_VECTOR (3 downto 0);
	signal ADC_Addr : STD_LOGIC_VECTOR (2 downto 0);
	signal ADCreg_D_int : STD_LOGIC_VECTOR (11 downto 0);

	signal PktCnt : STD_LOGIC_VECTOR (7 downto 0);
	signal SPI_SDO2, SPI_SDO1 : STD_LOGIC;

begin

	SPI_SCLK <= Clk;
	En <= stateQ(2) and not stateQ(1) and not stateQ(0);
	-- Define InitGo meant
	u1: Pulse_Delay port map (Clk, En, InitGo);

	u2: GetTempVal
	port map (Clk, Rst, InitGo, Tempreg_D, Done_Temp,
		  SPI_T_CE, SPI_SDO);--, ser_Go_u2, ser_D);
	Tempreg_En <= Done_Temp;

	ADC_Addr <= ChanCnt(2 downto 0);
	u3: GetADCval
	port map (Clk, Rst, Go_ADC, ADC_Addr, ADCreg_D_int, Done_ADC,
                  SPI_A_iCS, SPI_SDI, SPI_SDO, ser_Go,ser_D,db);

	Go_ADC <= (Done_Temp or Done_ADC_delayed) and En;
	ADCreg_En <= Done_ADC;
	ADCreg_A <= ADC_Addr when Done_ADC='1' else "ZZZ";
	ADCreg_D <= ADCreg_D_int;
		  
	--u4: c_dbldelay port map (Clk, Done_ADC, Done_ADC_delayed);
	u4: Counter4bit port map (Clk, Rst, Done_ADC, Done_ADC_delayed);

	addrinc : process (Rst,Done_ADC,En,InitGo) 
	begin
		if (Rst='1' or InitGo='1') then
			ChanCnt <= "0111";
		else
			if falling_edge(Done_ADC) and En='1' then
				ChanCnt <= ChanCnt - "0001";
			else
				ChanCnt <= ChanCnt;
			end if;
		end if;
	end process;


	Done_query <= '1' when (Done_ADC='1' and ChanCnt="1111") else '0';
	
	stateEn <= '1'   when (Done_query='1') else '0';
	stateD <=  "101" when (Done_query='1') else "ZZZ";
	
	cntpkts: process (Clk, Done_ADC, ChanCnt) begin
		if Rst='1' then
			PktCnt <= X"00";
		else
			if falling_edge(Clk) and InitGo='1' then
				PktCnt <= PktCnt + X"01";
			else
				PktCnt <= PktCnt;
			end if;
		end if;
	end process;
	
	ser_Go <= '0';--Done_ADC;
	--ser_D <= "0011" & Addr when Done='1' else "ZZZZZZZZ";
	--ser_D <= ADCreg_D_int(7 downto 0) when Done_ADC='1' else "ZZZZZZZZ";  
	--ser_D <= X"0" & ADCreg_D_int(11 downto 8) when Done_ADC='1' else "ZZZZZZZZ";  
	ser_D <= "ZZZZZZZZ";	
	
	--db <= dbsig;
end Behavioral;