----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    10/2009 
-- Design Name:    GetTempVal
-- Target Devices: Xilinx Spartan-3A
-- Tool versions:  Xilinx ISE 11.1
-- Description:    Fetches the 12bit value from specified channel on ADC
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity GetTempVal is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Go : in  STD_LOGIC;
           Q : out  STD_LOGIC_VECTOR (9 downto 0);
           Done : out  STD_LOGIC;

	   --SPI bus
           T_CE : out  STD_LOGIC;
           SDO   : in  STD_LOGIC;
			  
	   ser_Go : out STD_LOGIC;
	   ser_D : out STD_LOGIC_VECTOR (7 downto 0);
	   db : out STD_LOGIC
	 );
end GetTempVal;

architecture contr_arch of GetTempVal is

	signal cnt : STD_LOGIC_VECTOR (3 downto 0);
	signal En, En_sh : STD_LOGIC;
	signal Done_prep : STD_LOGIC;
	signal ReadTime : STD_LOGIC;
	signal reg : STD_LOGIC_VECTOR (9 downto 0);
	signal EnCnt : STD_LOGIC;

begin

	T_CE <= En;-- or En_sh;
	--u0: c_delay port map (Clk, En, En_sh);

	Readtime <= En and not (cnt(3) and cnt(2));

	procCtrl : process (Clk, Rst, Go, ReadTime) begin
		if Rst='1' then
			cnt <= "0000";
		else
			if falling_edge(Clk) then
				EnCnt <= cnt(3) or cnt(2) or cnt(1) or cnt(0);
				if Go='1' then
					En <= '1';
				else 
					if cnt="1110" then
						En <= '0';
					else
						En <= En;
					end if;
				end if;
				
				-- shift in values-----------
				if ReadTime='1' then
					for i in 0 to 8 loop
						reg(i+1) <= reg(i);
					end loop;
					reg(0) <= SDO;
				else
					reg(0) <= reg(0);
				end if;----------------------
			end if;
		
			if rising_edge(Clk) then
				cnt <= cnt + ("000" & (En or EnCnt));
			else
				cnt <= cnt;
			end if;
		end if;
	end process;
				
	Done_prep <= '1' when cnt="1110" else '0';
	u1: c_delay port map (Clk, Done_prep, Done);
	Q <= reg;
	
	db <= reg(0);
	ser_Go <= 'Z';--'1' when cnt="11100" else '0';
	--ser_D <= reg(7 downto 0) when cnt="11100" else "ZZZZZZZZ";
	ser_D <= "ZZZZZZZZ";

end contr_arch;