----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    10/2009 
-- Design Name:    GetADCval
-- Target Devices: Xilinx Spartan-3A
-- Tool versions:  Xilinx ISE 11.1
-- Description:    Fetches the 12bit value from specified channel on ADC
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity GetADCval is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;
           Go : in  STD_LOGIC;
           Addr : in  STD_LOGIC_VECTOR (2 downto 0);
           Q : out  STD_LOGIC_VECTOR (11 downto 0);
           Done : out  STD_LOGIC;

	   --SPI bus
           A_iCS : out  STD_LOGIC;
           SDI   : out  STD_LOGIC;
           SDO   : in  STD_LOGIC;
 
	   ser_Go : out STD_LOGIC;
	   ser_D : out STD_LOGIC_VECTOR (7 downto 0);
	   db : out STD_LOGIC
	 );
end GetADCval;

architecture contr_arch of GetADCval is

	signal cnt : STD_LOGIC_VECTOR (4 downto 0);
	signal En, En_sh, ReadTime, Done_prep, Done_int, SDI_int, NeedsReset : STD_LOGIC;
	
	signal Addr_Q : STD_LOGIC_VECTOR (2 downto 0);
	signal reg : STD_LOGIC_VECTOR (11 downto 0);

begin

	A_iCS <= '1' when cnt="10000" else not (En or Go);

	latchAddr : process (Clk,Go) begin
		if falling_edge(Clk) then
			if Go='1' then
				Addr_Q <= Addr;
			else
				Addr_Q <= Addr_Q;
			end if;
		end if;
	end process;

	procCtrl : process (Clk, Rst, Go) begin
		if Rst='1' then
			cnt <= "00000";
			NeedsReset <= '1';
			ReadTime <= '0';
			SDI_int <= '0';
		else
			if rising_edge(Clk) then
				if En='0' then
					cnt <= "00000";
				else
					cnt <= cnt + "00001";
				end if;
				
				-- shift in values-----------
				if ReadTime='1' then
					for i in 0 to 10 loop
						reg(i+1) <= reg(i);
					end loop;
					reg(0) <= SDO;
				else
					reg(0) <= reg(0);
				end if;----------------------

			else
				cnt <= cnt;
			end if;
			
			if falling_edge(Clk) then
				if Go='1' then
					En <= '1';
				elsif Done_int='1' then
					En <= '0';
				else
					En <= En;
				end if;
			end if;

			if En='0' then
				ReadTime <= '0';
			else
				if falling_edge(Clk) and cnt="10100" then
					ReadTime <= '1';
				else
					ReadTime <= ReadTime;
				end if;
			end if;

			
			case cnt(3 downto 0) is
				when "0011" => SDI_int <= Addr_Q(2);
				when "0100" => SDI_int <= Addr_Q(1);
				when "0101" => SDI_int <= Addr_Q(0);
				
				-- the following makes the first bit 1 and the last two "00"
				-- standing for "full range" and Two's complement encoding
				when others => SDI_int <= Go or (cnt(2) and cnt(1));
				-- ensures Wr bit on first convo + Pwr bits (ignored 2nd time)
			end case;
			
			if falling_edge(Clk) and cnt="11111" then 
				NeedsReset <= '0';
			else
				NeedsReset <= NeedsReset;
			end if;

		end if;
	end process;

	--SDI <= '1' when (Addr_Q="111" or NeedsReset='1') else SDI_int;
	SDI <= '1' when (NeedsReset='1') else SDI_int;
	
	Done_prep <= '1' when cnt="11111" else '0';
	u1: c_delay port map (Clk, Done_prep, Done_int);
	Done <= Done_int;
	Q <= reg;
	
	db <= reg(0);
	ser_Go <= 'Z';--'1' when cnt="11100" else '0';
	--ser_D <= reg(7 downto 0) when cnt="11100" else "ZZZZZZZZ";
	ser_D <= "ZZZZZZZZ";
end contr_arch;