----------------------------------------------------------------------------------
-- Company: Univserisy of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Date:				 8/11/2009 
-- Module Name:    wrToAddr - Behavioral_arch 
-- Description:    Commands the Transceiver->EthCtrl to write D to address A
--		   and return "Done" upon completion
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity wrToAddr is
    Port ( Clk : in  STD_LOGIC;
	   Rst : STD_LOGIC;
	   Go : in STD_LOGIC;                      -- pulse to start
	   A : in STD_LOGIC_VECTOR (7 downto 0);   -- address
	   D : in STD_LOGIC_VECTOR (7 downto 0);   -- data to be written
           -- Transceiver control lines
	   TxRx_Go : out  STD_LOGIC :='Z';
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0) := "ZZZZZZZZ";
           TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0) := "ZZZZZZZZ";
           TxRx_RiW : out  STD_LOGIC := 'Z';
	   TxRx_Done : in  STD_LOGIC;

	   Done : out STD_LOGIC -- signal of end of write (=TxRx_Done)
	 );
end wrToAddr;

architecture Behavioral_arch of wrToAddr is

	signal En : STD_LOGIC ;
	signal En_sh : STD_LOGIC;

begin 

	TxRx_Go <= Go;
	TxRx_A <= A when Go='1' else "ZZZZZZZZ";
	TxRx_D <= D when Go='1' else "ZZZZZZZZ";
	TxRx_RiW <= '0' when Go='1' else 'Z';   -- declare a write operation

	Done <= TxRx_Done and En_sh;

	Enable : process (Clk, Rst, TxRx_Done, En)
	begin
		if Rst='1' then
			En <= '0';
			En_sh <= '0';
		else

			if falling_edge(Clk) then
				if Go = '1' then
					En <= '1';
				else
					if TxRx_Done = '1' then
						En <= '0';
					else
						En <= En;
					end if;
				end if;
			end if;
			
			if rising_edge(Clk) then
				En_sh <= En;
			end if;

		end if;	
	end process;
	

end Behavioral_arch;