----------------------------------------------------------------------------------
-- Company: Univserisy of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    
-- Module Name:    wr2BtoAddr - Behavioral 
-- Description:    A wrapper for wrToAddr to write two bytes to consecutive memory 
--		   locations as is often necessary.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity wr2BtoAddr is
    Port ( Clk : in  STD_LOGIC;
	   Rst : in STD_LOGIC;
	   Go : in STD_LOGIC;
	   A : in STD_LOGIC_VECTOR (7 downto 0); 
	   D : in STD_LOGIC_VECTOR (15 downto 0);
           TxRx_Go : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_RiW : out  STD_LOGIC;
           TxRx_Done : in  STD_LOGIC;
	   Done : out STD_LOGIC
	 );
end wr2BtoAddr;

architecture Behavioral of wr2BtoAddr is

	component c_delay is
	    Port ( Clk : in  STD_LOGIC;
           	   D : in  STD_LOGIC;
           	   Q : out  STD_LOGIC
		 );
	end component;

	component Reg8bit is
	    Port ( Clk : in  STD_LOGIC;
           	   Rst : in  STD_LOGIC;
           	   En : in  STD_LOGIC;
           	   D : in  STD_LOGIC_VECTOR (7 downto 0);
           	   Q : out  STD_LOGIC_VECTOR (7 downto 0)
		 );
	end component;
	
	component wrToAddr is
	    Port ( Clk : in  STD_LOGIC;
		   Rst : STD_LOGIC;
		   Go : in STD_LOGIC;                      -- pulse to start
		   A : in STD_LOGIC_VECTOR (7 downto 0);   -- address
		   D : in STD_LOGIC_VECTOR (7 downto 0);   -- data to be written
            	   -- Transceiver control lines
		   TxRx_Go : out  STD_LOGIC;
           	   TxRx_A : out  STD_LOGIC_VECTOR;
           	   TxRx_D : out  STD_LOGIC_VECTOR;
           	   TxRx_RiW : out  STD_LOGIC;
		   TxRx_Done : in  STD_LOGIC;
		   Done : out STD_LOGIC -- signal of end of write (=TxRx_Done)
		 );
	end component;

	-- registers to hold params for writing
	signal Addr : STD_LOGIC_VECTOR (7 downto 0);
	signal Addr_reg : STD_LOGIC_VECTOR (7 downto 0);
	signal Data : STD_LOGIC_VECTOR (7 downto 0);
	signal Data_L : STD_LOGIC_VECTOR (7 downto 0);
	signal SecondByte : STD_LOGIC;

	-- states/pulses
	signal Go_Wr : STD_LOGIC;
	signal Done_Wr : STD_LOGIC;
	
begin

	-- write 8 MSB of Data to the passed in Addr.
	aH: wrToAddr
	port map (Clk, Rst, Go_Wr, Addr, Data,
		  TxRx_Go, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_Wr);

	r1: Reg8bit port map (Clk, Rst, Go_Wr, A, Addr_reg);

	-- remember the second byte before bus expires
	r2: Reg8bit port map (Clk, Rst, Go, D(7 downto 0), Data_L);

	cntWrites : process (Clk,Go)
	begin
		if Rst='1' or Go='1' then
			SecondByte<='0';
		else
			if rising_edge(Done_Wr) then
				SecondByte <= '1';
			end if;
		end if;
	end process;

	Addr <= Addr_reg+X"01" when Done_Wr='1' else A;
	Data <= D(15 downto 8) when Go='1' else Data_L;
	Go_Wr <= Go or (Done_Wr and not SecondByte);
	
	Done <= Done_Wr and SecondByte;

end Behavioral;






------------------------------------------------------------------



--architecture Behavioral2 of wr2BtoAddr is
--
--	component c_delay is
--	    Port ( Clk : in  STD_LOGIC;
--		   D : in  STD_LOGIC;
--		   Q : out  STD_LOGIC
--		 );
--	end component;
--
--	component Reg8bit is
--	    Port ( Clk : in  STD_LOGIC;
--		   Rst : in  STD_LOGIC;
--		   En : in  STD_LOGIC;
--		   D : in  STD_LOGIC_VECTOR (7 downto 0);
--		   Q : out  STD_LOGIC_VECTOR (7 downto 0)
--		 );
--	end component;
--	
--	component wrToAddr is
--	    Port ( Clk : in  STD_LOGIC;
--		   Rst : STD_LOGIC;
--		   Go : in STD_LOGIC;                      -- pulse to start
--		   A : in STD_LOGIC_VECTOR (7 downto 0);   -- address
--		   D : in STD_LOGIC_VECTOR (7 downto 0);   -- data to be written
--		   -- Transceiver control lines
--		   TxRx_Go : out  STD_LOGIC;
--		   TxRx_A : out  STD_LOGIC_VECTOR;
--		   TxRx_D : out  STD_LOGIC_VECTOR;
--		   TxRx_RiW : out  STD_LOGIC;
--		   TxRx_Done : in  STD_LOGIC;
--		   Done : out STD_LOGIC -- signal of end of write (=TxRx_Done)
--		 );
--	end component;
--
--	-- registers to hold params for writing
--	signal AddrL : STD_LOGIC_VECTOR (7 downto 0);
--	signal AddrL_reg : STD_LOGIC_VECTOR (7 downto 0);
--	signal Data : STD_LOGIC_VECTOR (7 downto 0);
--
--	-- states/pulses
--	signal Go_late : STD_LOGIC;
--	signal Done_AddrH : STD_LOGIC;
--	signal Done_data : STD_LOGIC;
--
--	signal TxRx_Go1 : STD_LOGIC;
--	signal TxRx_Go2 : STD_LOGIC;
--
--begin
--
--	-- write 8 MSB of Data to the passed in Addr.
--	aH: wrToAddr
--	port map (Clk, Rst, Go, A, D(15 downto 8), 
--		  TxRx_Go1, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_AddrH);
--
--	-- write 8 LSB of Data to the following address upon completion
--	aL: wrToAddr
--	port map (Clk, Rst, Done_AddrH, AddrL_reg, Data,
--		  TxRx_Go2, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_data);
--
--	TxRx_Go <= TxRx_Go1 or TxRx_Go2;
--
--	AddrL <= A + X"01";
--	r1: Reg8bit port map (Clk, Rst, Go, AddrL, AddrL_reg);
--
--	-- remember the second byte before bus expires
--	r2: Reg8bit port map (Clk, Rst, Go, D(7 downto 0), Data);
--
--
--	u1: c_delay port map (Clk, Done_data, Done);
--
--end Behavioral2;