---------------------------------------------------------------------------------- -- Company: Univserisy of Connecticut -- Engineer: Igor Senderovich -- -- Create Date: 03:08:15 10/09/2007 -- Module Name: reqFromAddr - Behavioral -- Description: Request from Transc.->EthCtrl data from specified address ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity reqFromAddr is Port ( Clk : in STD_LOGIC; Go : in STD_LOGIC; A : in STD_LOGIC_VECTOR (7 downto 0); TxRx_Go : out STD_LOGIC := 'Z'; TxRx_Aout : out STD_LOGIC_VECTOR (7 downto 0) := "ZZZZZZZZ"; TxRx_RiW : out STD_LOGIC := 'Z' ); end reqFromAddr; architecture Behavioral of reqFromAddr is component c_delay is Port ( Clk : in STD_LOGIC; D : in STD_LOGIC; Q : out STD_LOGIC ); end component; ---------------------------------------------------------------------------- -- Note: The version of the code commented out below -- guarantees data at TxRx_Go. Simplified current version expects -- latching on falling Clk edge in the middle of TxRx_Go pulse. ---------------------------------------------------------------------------- --signal Go_late : STD_LOGIC; --signal En : STD_LOGIC := 'Z'; --signal Addr : STD_LOGIC_VECTOR (7 downto 0); begin --u1: c_delay port map (Clk, Go, Go_late); --TxRx_Go <= '1' when Go_late='1' else 'Z'; TxRx_Go <= '1' when Go='1' else 'Z'; --TxRx_Aout <= Addr when En='1' else "ZZZZZZZZ"; TxRx_Aout <= A when Go='1' else "ZZZZZZZZ"; TxRx_RiW <= '1' when Go='1' else 'Z'; -- Enable : process (Go, Go_late) -- begin -- -- if (Go='1') then -- En <= '1'; -- --Addr <= A; -- else -- if (falling_edge(Go_late)) then -- En <= '0'; -- else -- En <= En; -- end if; -- --Addr <= Addr; -- end if; -- -- end process Enable; end Behavioral;