----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    22:57:00 10/11/2007 
-- Design Name: 
-- Module Name:    getByte_db - Behavioral 
-- Description:    Requests (via reqFromAddr module), receives and relays 
--		   one byte in the specified register of the 
--		   Ethernet Controller via the Transceiver.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity getByte_db is
    Port ( Clk : in  STD_LOGIC;
	   Rst : in  STD_LOGIC;
           Go : in  STD_LOGIC;
	   A : in STD_LOGIC_VECTOR (7 downto 0);
           Q : out  STD_LOGIC_VECTOR (7 downto 0);
           Done : out  STD_LOGIC;

           TxRx_Go : out  STD_LOGIC;
           TxRx_RiW : out  STD_LOGIC;
           TxRx_Aout : out  STD_LOGIC_VECTOR (7 downto 0);
	   TxRx_Din : in STD_LOGIC_VECTOR (7 downto 0);
           TxRx_Done : in  STD_LOGIC;
			  
	   db : out STD_ULOGIC
	 );
end getByte_db;

architecture Behavioral of getByte_db is

	component c_delay is
	    Port ( Clk : in  STD_LOGIC;
           	   D : in  STD_LOGIC;
           	   Q : out  STD_LOGIC
		 );
	end component;
	
	signal En : STD_LOGIC;
	signal Done_int : STD_LOGIC;
	signal En_sh : STD_LOGIC;
	signal db_int : STD_LOGIC;

begin

	TxRx_Go <= Go;

	--(silence on all buses when this module is not operating)
	TxRx_Aout <= A when Go='1' else "ZZZZZZZZ";
	TxRx_RiW <= '1' when Go='1' else 'Z';
	Q <= TxRx_Din when Done_int='1' else "ZZZZZZZZ";

	Done_int <= TxRx_Done and En_sh;
	Done <= Done_int;

	Enable : process (Clk, Rst, TxRx_Done, En)
	begin
		if Rst='1' then
			En <= '0';
			En_sh <= '0';
		else

			if falling_edge(Clk) then
				if Go = '1' then
					En <= '1';
				else
					if TxRx_Done = '1' then
						En <= '0';
					else
						En <= En;
					end if;
				end if;
			end if;
			
			if rising_edge(Clk) then
				En_sh <= En;
			end if;

		end if;	
	end process;

end Behavioral;