----------------------------------------------------------------------------------
-- Company: Univserisy of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    
-- Module Name:    RAwrToAddr - Behavioral 
-- Description:    Commands the Transc.->EthCtrl to write D to RamAddr in buffer
--		  (using random access method) '1' in MSB of RamAddr (being
--		   above the range) implies addr. increment from previous write.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity RAwrToAddr is
    Port ( Clk : in  STD_LOGIC;
	   Rst : in STD_LOGIC;
	   Go : in STD_LOGIC;
	   RamAddr : in STD_LOGIC_VECTOR (15 downto 0); -- AddrH:AddrL
	   D : in STD_LOGIC_VECTOR (7 downto 0);        -- Data

           TxRx_Go : out  STD_LOGIC :='Z';   -- Transceiver command lines
           TxRx_Aout : out  STD_LOGIC_VECTOR (7 downto 0) := "ZZZZZZZZ";
           TxRx_Dout : out  STD_LOGIC_VECTOR (7 downto 0) := "ZZZZZZZZ";
           TxRx_RiW : out  STD_LOGIC := 'Z';
           TxRx_Done : in  STD_LOGIC;
	   Done : out STD_LOGIC;

	   db : out STD_LOGIC
	 );
end RAwrToAddr;

architecture Behavioral of RAwrToAddr is

	-- registers to hold params for writing
	signal Addr : STD_LOGIC_VECTOR (15 downto 0);
	signal Data : STD_LOGIC_VECTOR (7 downto 0);

	-- states/pulses
	signal Go_late : STD_LOGIC;
	signal Done_Addr : STD_LOGIC;
	signal TxRx_Go_aH : STD_LOGIC;
	signal TxRx_Go_u2 : STD_LOGIC;

begin

	TxRx_Go <= TxRx_Go_aH or TxRx_Go_u2;

	u1: c_delay port map (Clk, Go, Go_late);

	-- move pointer: write RAMADDRH (0x08) and RAMADDRL (0x09) (latter implied) 
	aH: wr2BToAddr
	port map (Clk, Rst, Go_late, X"08", Addr, 
		  TxRx_Go_aH, TxRx_Aout, TxRx_Dout, TxRx_RiW, TxRx_Done, Done_Addr);
	db <= Done_Addr;

	-- write data to RAMTXDATA (0x04) on AddrL write completion
	u2: wrToAddr
	port map (Clk, Rst, Done_Addr, X"04", Data, 
		  TxRx_Go_u2, TxRx_Aout, TxRx_Dout, TxRx_RiW, TxRx_Done, Done);


	getparams : process (Rst, Clk)
	begin
		if (Rst='1') then
			Addr <= X"0000";
			Data <= X"00";
		else
			if (falling_edge(Clk)) then
				if (Go='1') then
					Data <= D;
					if (RamAddr(15)='1') then -- increment address
						Addr <= Addr + X"0001";
					else
						Addr <= RamAddr;  -- record a new write address
					end if;
				else
					Addr <= Addr;
					Data <= Data;
				end if;
			end if;
		end if;
	end process;

end Behavioral;