----------------------------------------------------------------------------------
-- Company: Univserisy of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    
-- Module Name:    RAwr2BtoAddr - Behavioral 
-- Description:    Wrapper for RAwrToAddr for writing 2-byte words. 
--		   this is convenient because most reported values are >8bit
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RAwr2BToAddr is
    Port ( Clk : in  STD_LOGIC;
	   Rst : in STD_LOGIC;
	   Go : in STD_LOGIC;
	   RamAddr : in STD_LOGIC_VECTOR (15 downto 0); -- AddrH:AddrL
	   D : in STD_LOGIC_VECTOR (15 downto 0);       -- 2 bytes of Data
           
	   RAwrGo   : out STD_LOGIC;
	   RAwrAddr : out STD_LOGIC_VECTOR (15 downto 0);
	   RAwrD    : out STD_LOGIC_VECTOR (7 downto 0);
	   RAwrDone : in  STD_LOGIC;
			  
--	   TxRx_Go : out  STD_LOGIC :='Z';   -- Transceiver command lines
--	   TxRx_Aout : out  STD_LOGIC_VECTOR (7 downto 0) := "ZZZZZZZZ";
--	   TxRx_Dout : out  STD_LOGIC_VECTOR (7 downto 0) := "ZZZZZZZZ";
--	   TxRx_RiW : out  STD_LOGIC := 'Z';
--	   TxRx_Done : in  STD_LOGIC;

	   Done : out STD_LOGIC
	 );
end RAwr2BtoAddr;

architecture Behavioral of RAwr2BtoAddr is

	component Reg8bit is
	    Port ( Clk : in  STD_LOGIC;
           	   Rst : in  STD_LOGIC;
           	   En : in  STD_LOGIC;
           	   D : in  STD_LOGIC_VECTOR (7 downto 0);
           	   Q : out  STD_LOGIC_VECTOR (7 downto 0)
		 );
	end component;

	-- states/pulses
	signal C : STD_LOGIC_VECTOR (1 downto 0); -- count stages
	signal Go_oncemore : STD_LOGIC;
	signal Data : STD_LOGIC_VECTOR (7 downto 0);

begin

--	u1: RAwrToAddr
--	port map (Clk, Rst, Go, RamAddr, D(15 downto 8), 
--		  TxRx_Go, TxRx_Aout, TxRx_Dout, TxRx_RiW, TxRx_Done, Go_oncemore);
	
	-- "Done" pulse counter from 01 - 11
	Coord : process (RAwrDone, Go, Rst)
	begin
		if (Go='1' or Rst='1') then
			C <= '0' & Go;
		else
			if (falling_edge(RAwrDone) and ((C(0) xor C(1))='1')) then
				C <= C + "01";
			else
				C <= C;
			end if;
		end if;
	end process;

	Go_oncemore <= RAwrDone and C(0) and not C(1);
	Done <= RAwrDone and C(1) and not C(0);
	
	RAwrGo <= Go or Go_oncemore;
	
	ByteNumberDecision : process (Go, Go_oncemore)
	begin
		if (Go='1' or Go_oncemore='1') then
			if Go = '1' then
				RAwrAddr <= RamAddr;
				RAwrD <= D(15 downto 8);
			else
				RAwrAddr <= X"F000";  -- on second byte just order Addr. increment
				RAwrD <= Data;
			end if;
		else 
			RAwrD <= "ZZZZZZZZ";
			RAwrAddr <= "ZZZZZZZZZZZZZZZZ";
		end if;
	end process;


	r1: Reg8bit port map (Clk, Rst, Go, D(7 downto 0), Data);


--	u2: RAwrToAddr
--	port map (Clk, Rst, Go_oncemore, X"F000", Data,
--		  TxRx_Go, TxRx_Aout, TxRx_Dout, TxRx_RiW, TxRx_Done, Done);

--	latchdata : process (Go)
--	begin
--		if (Go='1') then
--			Data <= D(7 downto 0);
--		else
--			Data <= Data;
--		end if;
--	end process;
		
end Behavioral;