----------------------------------------------------------------------------------
-- Company: Univserisy of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    03:08:15 10/09/2007 
-- Module Name:    MACwrToAddr - Behavioral_arch 
-- Description:    Commands the Transceiver->EthCtrl to write D to address A
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity MACwrToAddr is
    Port ( Clk : in  STD_LOGIC;
	   Rst : STD_LOGIC;
	   Go : in STD_LOGIC;                      -- pulse to start
	   A : in STD_LOGIC_VECTOR (7 downto 0);   -- indirect reg. address
	   D : in STD_LOGIC_VECTOR (15 downto 0);  -- data to be written
           -- Transceiver control lines
	   TxRx_Go : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_D : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_RiW : out  STD_LOGIC := 'Z';
	   TxRx_Done : in  STD_LOGIC;

	   Done : out STD_LOGIC;
	   db : out STD_LOGIC
	 );
end MACwrToAddr;

architecture Behavioral_arch of MACwrToAddr is
	
	signal Done_SetMACAddr : STD_LOGIC ;
	signal Done_1stByte : STD_LOGIC;
	signal Done_MAC2B : STD_LOGIC;
	
	signal TxRx_Go1 : STD_LOGIC;
	signal TxRx_Go2a : STD_LOGIC;	signal TxRx_Go2b : STD_LOGIC;
	signal TxRx_Go3 : STD_LOGIC;

begin

	-- Set MACADDR to the proper indirect 16-bit register
	m1: wrToAddr
	port map (Clk, Rst, Go, X"0A", A,
		  TxRx_Go1, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_SetMACAddr);

	-- write 16-bit data from D into the (consecutive) MACDATAH:MACDATAL
--	m2: wr2BtoAddr
--	port map (Clk, Rst, Done_SetMACAddr, X"0B", D,
--		  TxRx_Go2a, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_MAC2B);

	m2a: wrToAddr
	port map (Clk, Rst, Done_SetMACAddr, X"0B", D(15 downto 8),
		  TxRx_Go2a, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_1stByte);

	m2b: wrToAddr
	port map (Clk, Rst, Done_1stByte, X"0C", D(7 downto 0),
		  TxRx_Go2b, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done_MAC2B);
	
	-- send this off by writing to MACRW (0x0D)
	m3: wrToAddr
	port map (Clk, Rst, Done_MAC2B, X"0D", X"FF",
		  TxRx_Go3, TxRx_A, TxRx_D, TxRx_RiW, TxRx_Done, Done);

	TxRx_Go <= TxRx_Go1 or TxRx_Go2a or TxRx_Go2b or TxRx_Go3;
	
end Behavioral_arch;