----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:   22:52:57 11/29/2007
-- Design Name: 
-- Module Name:   INTCatcher - Behavioral 
-- Description:   Polls the interrupt registers of the Ethernet Controller
--		  until an interrupt which matches that specified in the Mask
--		  if found and returns Done.
--		  Mask (in order from MSB to LSB) picks out:
--			3- INT0(6) Receive FIFO Empty
--			2- INT0(5) Self Init. Complete
--			1- INT0(4) Oscillator Init. Complete
--			0- INT1(2) Auto-Negotation failed
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity INTCatcher is
    Port ( Clk : in  STD_LOGIC;
	   Rst : in STD_LOGIC;
	   Eth_iINT: in STD_LOGIC;
           Go : in  STD_LOGIC;
           Mask : in  STD_LOGIC_VECTOR(7 downto 0); --INT flag mask
           INTs : out  STD_LOGIC_VECTOR(7 downto 0); 			  
	   Done : out STD_LOGIC;

	  --Transceiver control lines
	   TxRx_Go : out  STD_LOGIC;
           TxRx_A : out  STD_LOGIC_VECTOR (7 downto 0);
           TxRx_RiW : out  STD_LOGIC;
	   TxRx_Q : in  STD_LOGIC_VECTOR (7 downto 0);
	   TxRx_Done : in  STD_LOGIC;

  	   ser_Go : out STD_LOGIC;
  	   ser_D : out STD_LOGIC_VECTOR (7 downto 0);

	   db : out STD_LOGIC
	 );
end INTCatcher;

architecture Behavioral of INTCatcher is

	signal Data, Data_INT0, Data_INT1, INTs_D : STD_LOGIC_VECTOR (7 downto 0);
	signal En : STD_LOGIC;	--signal En_delayed : STD_LOGIC;
	signal INT : STD_LOGIC;
	signal INTfound : STD_LOGIC;
	signal INTdelayed : STD_LOGIC;
	signal Go_Query : STD_LOGIC;
	signal Done_INT0, Done_PhySTA, Done_INT1, Done_INT0_delayed, Done_int : STD_LOGIC;	
	signal TxRx_Go_INT0, TxRx_Go_INT1, TxRx_Go_PhySta : STD_LOGIC;	
	
	signal ser_LogStr : STRING (1 to dbSTRLEN);
	signal INTval1, INTval2 : INTEGER range 1 to 8;
	signal INTname1, INTname2 : STRING (1 to 12);
	
	signal Go_INT2 : STD_LOGIC;
	signal CombRep : STD_LOGIC_VECTOR (5 downto 0);
	--signal SerChar : STD_LOGIC_VECTOR (7 downto 0);

begin

--	db1: SerStringOut port map (Clk, Rst,Go_ser, ser_LogStr, db_serial,Done);--,db);
--	ser_LogStr <= "IRQ: " & INTname1 & " " & INTname2;
--	ser_LogStr <= "IRQ: polling .................";

--	db2: SerialOut port map (Clk, Rst, Go_ser_rethought, SerChar, db_serial,Done);

--	Done <= Done_INT1;
	TxRx_Go <= TxRx_Go_INT0 or TxRx_Go_INT1 or TxRx_Go_PhySta;
	db <= Data(3);
	
	CtrlProc : process (Rst,Go,INTfound)
	begin
		if (Rst='1') then
			En <= '0';
		else
			if (Go='1') then
				En <='1';
			else
				if rising_edge(INTfound) then
					En <= '0';
				else 
					En <= En;
				end if;
			end if;
		end if;
	end process;

	
	INT <= not Eth_iINT and En;
	u0: c_delay port map (Clk, INT, INTdelayed);
	u1: pulser port map (Clk, INTdelayed, Go_Query);
		
	-- Read INT1
	u2: getByte
	port map (Clk, Rst, Go_Query, X"63", Data, Done_INT0,
		  TxRx_Go_INT0, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done);

	r1: Reg8bit
	port map (Clk, Rst, Done_INT0, Data, Data_INT0);

--	u2b: getByte
--	port map (Clk, Rst, Done_INT0, X"80", Data, Done_PhySTA,
--		  TxRx_Go_PhySta, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done);

	u3: getByte
	port map (Clk, Rst, Done_INT0, X"7F", Data_INT1, Done_INT1,
		  TxRx_Go_INT1, TxRx_RiW, TxRx_A, TxRx_Q, TxRx_Done);

	r2: Reg8bit
	port map (Clk, Rst, Done_INT1, INTs_D, INTs);
	INTs_D <= "00" & Data_INT0(5 downto 4) & Data_INT1(2)
		       & Data_INT0(2) & Data_INT1(0) & Data_INT0(0); 
 
	INTfound <= Done_INT1 ;	
	u4: c_dbldelay port map (Clk, Done_INT1, Done);
	--u4: Counter16bit port map (Clk, Rst, Done_INT1, Done);


	ser_Go <= Done_INT1 or Done_PhySTA;
	ser_D <= ("01" & CombRep) when Done_INT1='1' else 
				--Data when Done_PhySTA='1' else 
				"ZZZZZZZZ";
	CombRep <= Data_INT0(5 downto 4) & Data_INT1(2) & Data_INT0(2)
				         & Data_INT1(0) & Data_INT0(0); 
	
	
end Behavioral;
-------------------------------------------------------




--	function LitBit (D : STD_LOGIC) return character is begin
--	 	if D = '1' then
--			return '1';
--		else
--			return '0';
--		end if;
--	 end;
--
--	FUNCTION Lit8bit ( LogicVector : std_logic_vector) RETURN string IS
--		variable str : STRING (8 downto 1);
--	BEGIN
--		for i in 7 downto 0 loop
--			str(i+1) := LitBit(LogicVector(i));
--		end loop;
--		RETURN str;
--	END;