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-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    15:02:01 06/19/2007 
-- Design Name: 19-Cycle Hold Component for DAC Emulator
-- Module Name:    DAC_hold19 - DAC_hold_arch 
-- Project Name: Readout Electronics Digital Board
-- Target Devices: no devices; for testing of other designs
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: Receives an active-low one-clock-cycle-long pulse, outputs an
--						active-high 19-clock-cycle-long pulse
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DAC_hold19 is
    Port ( CLK : in STD_LOGIC; -- clock
	   invReset : in STD_LOGIC; -- asynchronous, active-low reset line
	   invBegin : in STD_LOGIC; -- active-low pulse to begin
           Go : out STD_LOGIC -- 19-cycle hold output
	 );
end DAC_hold19;

architecture DAC_hold_arch of DAC_hold19 is

	signal count : STD_LOGIC_VECTOR(4 downto 0); -- internal counter

begin

	count_to_19 : process (CLK, invBegin, invReset)
	begin
		if (invReset = '0') then
			-- asynchronous, active-low reset
			count <= "00000";
		else
			if (falling_edge(CLK)) then
				if (count = "00000") then
					-- begin count only on active-low pulse
					if (invBegin = '0') then
						count <= count + 1;
					else
						count <= count;
					end if;
				else
					-- continue count for 19 cycles, ignoring further input
					if (count = 19) then
						count <= "00000";
					else
						count <= count + 1;
					end if;
				end if;
			else
				count <= count;
			end if;
		end if;
	end process count_to_19;
	
	-- hold the output high while counting, drop when counter returns to zero
	Go <= count(0) or count(1) or count(2) or count (3) or count(4);

end DAC_hold_arch;