----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    13:48:12 06/20/2007 
-- Design Name: Controller for Analog Devices' AD5535 DAC
-- Module Name:    DAC_controller - DAC_control_arch 
-- Project Name: Readout Electronics Digital Board
-- Target Devices: Xilinx Spartan-3A
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: Control block to communicate with DAC over serial interface
--
-- Dependencies: 
--
-- Revision:  Igor Senderovich
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity DAC_controller is
    Port ( CLK : in  STD_LOGIC;  -- clock
	   invRst : in  STD_LOGIC; -- asynchronous, active-low reset for controller
           invTxGo : in  STD_LOGIC; -- active-low start of transmission pulse
           Addr : in  STD_LOGIC_VECTOR (4 downto 0); -- 5-bit address
           Code : in  STD_LOGIC_VECTOR (13 downto 0); -- 14-bit code
           invSYNC : out  STD_LOGIC; -- /SYNC
           Data : out  STD_LOGIC; -- D_in
	   Done : out STD_LOGIC
	 );
end DAC_controller;

architecture DAC_control_arch of DAC_controller is

	-- declaring component wrappers
	component c_delay
	    Port ( CLK : in STD_LOGIC;
		   D : in STD_LOGIC;
		   Q : out STD_LOGIC
		 );
	end component;

	component Pulser
	    Port ( CLK : in STD_LOGIC;
		   D : in STD_LOGIC;
	 	   Q : out STD_LOGIC
		 );
	end component;

	component DAC_hold19
	    Port ( CLK : in STD_LOGIC;
	  	   invReset : in STD_LOGIC;
		   invBegin : in STD_LOGIC;
		   Go : out STD_LOGIC
		 );
	end component;
	
	component DAC_shiftreg
	    Port ( CLK  : in  STD_LOGIC;
		   invRST : in  STD_LOGIC;
		   Addr : in  STD_LOGIC_VECTOR (4 downto 0);
		   Code : in  STD_LOGIC_VECTOR (13 downto 0);
		   Sh_iRd : in  STD_LOGIC;
		   Q : out  STD_LOGIC
		 );
	end component;
	
	signal shift : STD_LOGIC;
	--signal ishift : STD_LOGIC;
	--signal Done_shift : STD_LOGIC;
	--signal invSync_int : STD_LOGIC;
	--signal iGo_hold : STD_LOGIC;

	--signal Addr_int : STD_LOGIC_VECTOR (4 downto 0);
	--signal Code_int : STD_LOGIC_VECTOR (13 downto 0);
	signal Reg : STD_LOGIC_VECTOR (18 downto 0);				-- internal register value
	signal cnt : integer range 20 downto 0;
begin
	
	LatchData : process (Clk, invTxGo,shift, invRst)
	begin
		if (invRst='0') then
			Reg <= "0000000000000000000";
		else
			if falling_edge(Clk) then
				if (invTxGo='0') then
					Reg <= Addr & Code;
					cnt <= 19;
				else
					if shift='1' then
						cnt <= cnt - 1;
					else
						cnt <= cnt;
					end if;
				end if;
			else
				Reg <= Reg;
			end if;
		end if;	
	end process;
	
	shift <= '1' when cnt/=0 else '0';
	
	ShiftData : process (Clk, shift, cnt)
	begin
		if rising_edge(CLK) then
			if shift='1' then
				Data <= Reg(cnt-1);
			else
				Data <= '0';
			end if;
			
			if cnt=1 then
				Done <= '1';
			else
				Done <= '0';
			end if;
		end if;
	end process;
	
	-- port maps to include components
	--u1: DAC_hold19		port map (CLK, invRst, invTxGo, shift);
	--u2: DAC_shiftreg	port map (CLK, invRst, Addr, Code, shift, Data);
	u3: c_delay			port map (CLK, invTxGo, invSync);
	--invSync <= invSync_int;
	
	-- Done signal
	--ishift <= not shift;
	--u4: Pulse_Delay   port map (CLK, ishift, Done_shift);
	--u4: Pulser        port map (CLK, ishift, Done_shift);
	--u5: c_delay       port map (CLK, Done_shift, Done);

	-- (uncomment if not wired by FPGA_ctrl)
	-- connect feed-through signals
	--SCLK <= CLK;
	--invDRst_out <= invDRst_in;

end DAC_control_arch;