---------------------------------------------------------------------------------- -- Company: University of Connecticut -- Engineer: Igor Senderovich -- -- Create Date: 12:14:27 10/28/2009 -- Module Name: ConfigParam - Behavioral -- Description: FPGA firmware fixed parameter file -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ConfigParam is Port ( DAC_Qmax : out STD_LOGIC_VECTOR (13 downto 0); DAC_Q_GainModeChan : out STD_LOGIC_VECTOR (13 downto 0); dbShort : out STD_LOGIC); end ConfigParam; architecture Behavioral of ConfigParam is begin -- IMPORTANT: the following sets the maximum allowed -- DAC output voltage. Conversion from voltage units: -- DAC_Qmax = Vmax * 2^14/(Vref*50) -- original board design: Vref=3.3V DAC_Qmax <= "01111001000001"; -- = 78V @ Vref=3.3V --DAC_Qmax <= "00111111100111"; -- = 41V @ Vref=3.3V --DAC_Qmax <= "11010001111010"; -- = 41V @ Vref=1.0V --DAC_Qmax <= "01100110011001"; -- = 20V @ Vref=1.0V --DAC_Qmax <= "11111111111111"; -- = supply is the limit --DAC_Qmax <= "01111111111111"; -- = 25V @ Vref=1.0V -- Here we set the binary value corresponding to the 5V -- Gain Mode selector channel. As described above, this -- binary value depends on the Vref. -- Also, due to systematics in the DAC at low voltages, -- greater than 5V values may be used, relying on the -- Zener diode to limit the voltage at 5V -- (refer to the diode's spec sheet for maximum allowed) --DAC_Q_GainModeChan <= "00100011110101"; -- = 7V @ Vref=1.0V --DAC_Q_GainModeChan <= "00001010110111"; -- = 7V @ Vref=3.3V --DAC_Q_GainModeChan <= "00101110100010"; -- = 30V @ Vref=3.3V DAC_Q_GainModeChan <= "00010001000100"; -- = 11V @ Vref=3.3V -- shorts out the mandatory long waiting times when set to '1' -- e.g. during Eth. Ctrl physical layer startup -- Used only as a convenience for simulations. dbShort <= '0'; end Behavioral;