----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    17:05:48 07/17/2007 
-- Design Name: SPI Controller
-- Module Name:    SPIctrl - contr_arch 
-- Project Name: SPI Module
-- Target Devices: Xilinx Spartan-3A
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: SPI bus master; controls ADC and temperature sensor.
--              Triggers ADC (pick a 3-bit chan.) or Temp data acquisition on "Go"
--              Expects T_iA chip select (1 - Temp, 0 - ADC)
--                 to be held for the duration of the operation
--              On completion, writes to the appropriate bus and declares "Done"
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity SPIctrl is
    Port ( ---- Input ----
			  Clk : in  STD_LOGIC;
           iRst_in : in  STD_LOGIC;
           T_iA : in  STD_LOGIC;
           Go : in  STD_LOGIC;
           Addr : in  STD_LOGIC_VECTOR (2 downto 0);
           SDO : in  STD_LOGIC;
			  ---- Output ----
           SCLK : out  STD_LOGIC;
           iRst_out : out  STD_LOGIC;
           SDI : out  STD_LOGIC;
           T_CE : out  STD_LOGIC;
           A_iCS : out  STD_LOGIC;
           Done : out  STD_LOGIC;
           T_Q : out  STD_LOGIC_VECTOR (9 downto 0);
           A_A : out  STD_LOGIC_VECTOR (2 downto 0);
           A_Q : out  STD_LOGIC_VECTOR (11 downto 0);
			  
			  ser_Go : out STD_LOGIC;
			  ser_D : out STD_LOGIC_VECTOR (7 downto 0);
			  db : out STD_LOGIC
			  );
end SPIctrl;

architecture contr_arch of SPIctrl is

	component c_count is
		Port ( Clk : in  STD_LOGIC;
				 iRst : in  STD_LOGIC;
				 Go : in  STD_LOGIC;
				 CE : out  STD_LOGIC;
				 Done : out  STD_LOGIC);
	end component;
	
	component c_enable is
		Port ( Clk : in  STD_LOGIC;
				 T_iA : in  STD_LOGIC;
				 CE : in  STD_LOGIC;
				 T_CE : out  STD_LOGIC;
				 A_iCS : out  STD_LOGIC);
	end component;
	
	component c_flipflop is
		Port ( Clk : in  STD_LOGIC;
				 iRst : in  STD_LOGIC;
				 En : in  STD_LOGIC;
				 D : in  STD_LOGIC;
				 Q : out  STD_LOGIC);
	end component;
	
	component c_selector is
		Port ( Clk : in  STD_LOGIC;
				 iRst : in  STD_LOGIC;
				 En : in  STD_LOGIC;
				 Sel : in  STD_LOGIC;
				 D : in  STD_LOGIC_VECTOR (15 downto 0);
				 T_Q : out  STD_LOGIC_VECTOR (9 downto 0);
				 A_A : out  STD_LOGIC_VECTOR (2 downto 0);
				 A_Q : out  STD_LOGIC_VECTOR (11 downto 0));
	end component;
	
	component c_shift_in16 is
		Port ( Clk : in  STD_LOGIC;
				 iRst : in  STD_LOGIC;
				 Sh : in  STD_LOGIC;
				 D : in  STD_LOGIC;
				 Q : out  STD_LOGIC_VECTOR (15 downto 0));
	end component;
	
	component c_shift_out12 is
		Port ( Clk : in  STD_LOGIC;
				 iRst : in  STD_LOGIC;
				 Sh_Ld : in  STD_LOGIC;
				 D_W : in  STD_LOGIC;
				 D_A : in  STD_LOGIC_VECTOR (8 downto 6);
				 Q : out  STD_LOGIC);
	end component;

	component c_A_proccontrol is
		Port ( Clk : in  STD_LOGIC;
				 iRst : in  STD_LOGIC;
				 iEn : in  STD_LOGIC;
				 Go : in  STD_LOGIC;
				 T_iA : in STD_LOGIC;
				 CycDone : in STD_LOGIC;
				 Addr : in  STD_LOGIC_VECTOR (2 downto 0);
				 A_A : in  STD_LOGIC_VECTOR (2 downto 0);
				 Go_int : out STD_LOGIC;
				 Wr : out  STD_LOGIC;
				 Addr_int: out STD_LOGIC_VECTOR (2 downto 0);
				 Done : out STD_LOGIC);
	end component;

	component c_ADCreset is
		Port ( Clk : in  STD_LOGIC;
           iRst : in  STD_LOGIC;
           T_iA : in STD_LOGIC;
           Done : in STD_LOGIC;
			  Go : out STD_LOGIC;
           T_iA_int : out STD_LOGIC
			  );
	end component;

	
	signal CE1 : STD_LOGIC;
	signal CE2 : STD_LOGIC;
	signal T_iA1 : STD_LOGIC;
	signal T_iA2 : STD_LOGIC;
	signal CycDone : STD_LOGIC;
	signal data : STD_LOGIC_VECTOR (15 downto 0);

	signal Wr: STD_LOGIC;
	signal A_A_int: STD_LOGIC_VECTOR (2 downto 0);
	signal Addr_int: STD_LOGIC_VECTOR (2 downto 0);
	signal Go_int : STD_LOGIC;
	signal Done_int : STD_LOGIC;
	signal Go_rst : STD_LOGIC;
	signal Go_norm : STD_LOGIC;

	signal SDI_int : STD_LOGIC;
	signal iCS : STD_LOGIC;


begin
	SCLK <= Clk;
	iRst_out <= iRst_in; --pass it through, just in case

	u1: c_count			port map (Clk, iRst_in, Go_int, CE1, CycDone);
	--u2: c_delay			port map (Clk, CE1, CE2);
	halfWvDelay : process(Clk) begin
		if falling_edge(Clk) then CE2 <= CE1;
		else CE2 <= CE2; end if;
	end process;
		
	--u3: c_enable		port map (Clk, T_iA1, CE1, T_CE, A_iCS);
	iCS <= not CE1 or T_iA1;
	u3 : c_delay port map (Clk, iCS, A_iCS);
	T_CE <= CE1 and T_iA1;


	u4: c_flipflop		port map (Clk, iRst_in, Go_int, T_iA1, T_iA2);
	u5: c_selector		port map (Clk, iRst_in, CycDone, T_iA2, data, T_Q, A_A_int, A_Q);
	u6: c_shift_in16	port map (Clk, iRst_in, CE2, SDO, data);
	u7: c_shift_out12	port map (Clk, iRst_in, CE1, Wr, Addr_int, SDI_int);

	u8: c_A_proccontrol port map(Clk, iRst_in, Go_rst, 
											Go, T_iA1, CycDone, Addr, A_A_int,
											Go_norm, Wr, Addr_int, Done_int);

	u9: c_ADCreset    port map(Clk, iRst_in, T_iA, CycDone, 
											Go_rst, T_iA1);

	Go_int <= Go_norm or Go_rst;
	SDI <= SDI_int or Go_rst;

	A_A <= A_A_int;

	db <= SDO;
	Done <= Done_int;
--	ser_Go <= Go_norm;
--	ser_D <= Addr_int
end contr_arch;