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-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    16:58:55 07/17/2007 
-- Design Name: Flip-Flop for SPI Controller
-- Module Name:    c_flipflop - c_flipflop_arch 
-- Project Name: SPI Module
-- Target Devices: Xilinx Spartan-3A
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: A flip-flop with reset and enable.  Used to save Temp/ADC line.
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity c_flipflop is
    Port ( Clk : in  STD_LOGIC;
           iRst : in  STD_LOGIC;
			  En : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end c_flipflop;

architecture c_flipflop_arch of c_flipflop is

	signal ff : STD_LOGIC;

begin

	flipflop : process (Clk, iRst)
	begin
		if (iRst = '0') then
			ff <= '0';
		else
			if (rising_edge(Clk)) then
				if (En = '1') then
					ff <= D;
				else
					ff <= ff;
				end if;
			else
				ff <= ff;
			end if;
		end if;
	end process flipflop;
	
	Q <= ff;

end c_flipflop_arch;