----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    16:49:13 07/17/2007 
-- Design Name: Enable Line Manager for SPI Controller
-- Module Name:    c_enable - c_enable_arch 
-- Project Name: SPI Module
-- Target Devices: Xilinx Spartan-3A
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: Mixes multiple signals to assemble chip select/chip enable lines
--		on SPI bus with proper timing.
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity c_enable is
    Port ( Clk : in  STD_LOGIC;
           T_iA : in  STD_LOGIC;
           CE : in  STD_LOGIC;
           T_CE : out  STD_LOGIC;
           A_iCS : out  STD_LOGIC);
end c_enable;

architecture c_enable_arch of c_enable is

	component c_delay is
		Port ( Clk : in  STD_LOGIC;
				 D : in  STD_LOGIC;
				 Q : out  STD_LOGIC);
	end component;

	signal iCS : STD_LOGIC;

begin

	iCS <= not CE or T_iA;
	u1 : c_delay port map (Clk, iCS, A_iCS);
	T_CE <= CE and T_iA;

end c_enable_arch;