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-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    16:15:18 07/17/2007 
-- Design Name: Counter for SPI Controller
-- Module Name:    c_count - c_count_arch 
-- Project Name: SPI Module
-- Target Devices: Xilinx Spartan-3A
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: A 5-bit counter.  Idles until receiving a pulse on "Go"; counts
--		for 16 cycles ("CE" asserted); pauses for one cycle; counts for one cycle
--		("Done" asserted); returns to idle.
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity c_count is
    Port ( Clk : in  STD_LOGIC;
           iRst : in  STD_LOGIC;
           Go : in  STD_LOGIC;
           CE : out  STD_LOGIC;
           Done : out  STD_LOGIC);
end c_count;

architecture c_count_arch of c_count is

	signal count : STD_LOGIC_VECTOR (4 downto 0);

begin

	counter : process (Clk, iRst, Go)
	begin
		if (iRst = '0') then
			count <= "00010";
		else
			if (rising_edge(Clk)) then
				if (count = "00010") then
					if (Go = '1') then
						count <= "10000";
					else
						count <= count;
					end if;
				else
					count <= count + 1;
				end if;
			else
				count <= count;
			end if;
		end if;
	end process counter;
	
	CE <= count(4);
	Done <= not count(4) and count(0);

end c_count_arch;