----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    16:15:18 07/17/2007 
-- Design Name: Counter for SPI Controller
-- Module Name:    c_ADCreset - c_ADCreset_arch 
-- Project Name: SPI Module
-- Target Devices: Xilinx Spartan-3A
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description:  A reset module to be activated on powerup to give the ADC the
--                  required 2 dummy cycles on ones in the control buffer.
--                  
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity c_ADCreset is
    Port ( Clk : in  STD_LOGIC;
           iRst : in  STD_LOGIC;
           T_iA : in STD_LOGIC;
           Done : in STD_LOGIC;
			  
			  Go : out STD_LOGIC;
           T_iA_int : out STD_LOGIC
			  );
end c_ADCreset;

architecture c_ADCreset_arch of c_ADCreset is

	signal RstCyc : STD_LOGIC;
	signal CycNum : STD_LOGIC;

begin

	resetcounter : process (Clk, iRst, T_iA, Done, RstCyc,CycNum)
	begin
		if (iRst = '0') then 
			RstCyc <= '1'; -- begin reset cycle
			CycNum <= '0'; -- mark 1st dummy cycle
		else
			if (falling_edge(Clk)) then
				if (RstCyc = '1') then
					if (Done = '1') then
						if (CycNum = '0') then -- begin 2nd dummy cyc.
							CycNum <= '1';
							RstCyc <= RstCyc;
						else -- end of 2nd dummy cyc -> end of reset.
							RstCyc <= '0';
							CycNum <= '0';
						end if;
					else -- continue holding values
						CycNum <= CycNum;	RstCyc <= RstCyc;
					end if;
					
				else
					CycNum <= CycNum; RstCyc <= RstCyc;
				end if;
			
			else
				RstCyc <= RstCyc; CycNum <= CycNum;
			end if;
		end if;

	end process resetcounter;	

	T_iA_int <= '0' when RstCyc='1' else T_iA;
	Go <= RstCyc;

end c_ADCreset_arch;