----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    22:08:21 09/30/2007 
-- Design Name: 
-- Module Name:    Idler_ctrl - Behavioral 
-- Description: 	Idles, while waiting for "Packet Arrived" interrupt from the 
--							Ethernet Controller chip, at which point
--							it yields control to state 011 - packet reading.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library FPGA_BasicComp;
use FPGA_BasicComp.BasicComp.all;

entity Idler_ctrl is
    Port ( Clk : in  STD_LOGIC;
           Rst : in  STD_LOGIC;

           state_En : out  STD_LOGIC;
           state_D : out  STD_LOGIC_VECTOR (2 downto 0);
           state_Q : in  STD_LOGIC_VECTOR (2 downto 0);

			  --Interrupt catcher control lines
			  INT_Go		: out STD_LOGIC;
			  INT_Mask	: out STD_LOGIC_VECTOR (7 downto 0);
			  INT_Found	: in STD_LOGIC_VECTOR (7 downto 0);
			  INT_Done	: in STD_LOGIC;
			  
  			  db : out STD_LOGIC
			);
end Idler_ctrl;

architecture Behavioral of Idler_ctrl is

	signal Data : STD_LOGIC_VECTOR (7 downto 0);
	signal InitGo, Go, En, PacketArrived, INT_occurred : STD_LOGIC;

begin

	En <= not state_Q(2) and state_Q(1) and not state_Q(0);
	u1: Pulse_Delay port map (Clk, En, InitGo); 

	Go <= InitGo or (INT_occurred and not INT_Found(0));
	g4: Trigger port map (Rst, Go, INT_Done, INT_occurred);
	INT_Go <= Go;
	INT_Mask <= "00000000" when Go='1' else "ZZZZZZZZ";
	PacketArrived <= INT_occurred and INT_Found(0);


	state_En <= PacketArrived;
	state_D <= "011" when (PacketArrived='1') else "ZZZ";

	db <= INT_occurred;
end Behavioral;