----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    13:25:24 06/20/2007 
-- Design Name: Shift Register for DAC Controller
-- Module Name:    DAC_shiftreg - DAC_shiftreg_arch 
-- Project Name: Readout Electronics Digital Board
-- Target Devices: Xilinx Spartan-3A
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: parallel-in, serial-out shift register with asynchronous reset,
--						loads when not shifting
--
-- Dependencies: 
--
-- Revision: Igor Senderovich
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DAC_shiftreg is
    Port ( CLK		:	in		STD_LOGIC;								-- clock line
			  invRST	:	in		STD_LOGIC;								-- asynchronous, active-low reset
           Addr	:	in		STD_LOGIC_VECTOR (4 downto 0);	-- 5-bit address
           Code	:	in		STD_LOGIC_VECTOR (13 downto 0);	-- 14-bit code
           Sh_iRd	:	in		STD_LOGIC;								-- active-high shift enable, active-low read enable
           Q		:	out 	STD_LOGIC);								-- output
end DAC_shiftreg;

architecture DAC_shiftreg_arch of DAC_shiftreg is

	signal SReg : STD_LOGIC_VECTOR (18 downto 0);				-- internal register value
	signal LineOut : STD_LOGIC;										-- output line

begin

	shift : process (CLK, invRST, Sh_iRd, Addr, Code)
	begin
		if (invRST = '0') then
			-- asynchronous, active-low reset line
			SReg <= "0000000000000000000";
			LineOut <= '0';
		else
			if (Sh_iRd = '0') then	-- read, no output
				SReg <= Addr & Code;
				LineOut <= '0';
			else
				if rising_edge(CLK) then	-- shift output, no read
					LineOut <= SReg(18);	
					for i in 0 to 17 loop
						SReg(i+1) <= SReg(i);
					end loop;
					SReg(0) <= '0';
				else
					SReg <= SReg;
					LineOut <= LineOut;
				end if;
			end if;
--			if (rising_edge(CLK)) then
--				if (Sh_iRd = '0') then		-- read, no output
--					SReg <= Addr & Code;
--					LineOut <= '0';
--				else								-- shift output, no read
--					LineOut <= SReg(18);
--					for i in 0 to 17 loop
--						SReg(i+1) <= SReg(i);
--					end loop;
--					SReg(0) <= '0';
--				end if;
--			else
--				SReg <= SReg;
--				LineOut <= LineOut;
--			end if;
		end if;
	end process shift;
	
	Q <= LineOut;		-- connect output line to output pin

end DAC_shiftreg_arch;