----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Brendan Krueger
-- 
-- Create Date:    13:48:12 06/20/2007 
-- Design Name: Controller for Analog Devices' AD5535 DAC
-- Module Name:    DAC_controller - DAC_control_arch 
-- Project Name: Readout Electronics Digital Board
-- Target Devices: Xilinx Spartan-3A
-- Tool versions: Xilinx ISE WebPACK 9.1.03i
-- Description: Control block to communicate with DAC over serial interface
--
-- Dependencies: 
--
-- Revision:  Igor Senderovich
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DAC_controller is
    Port ( CLK : in  STD_LOGIC;  -- clock
			  invRst : in  STD_LOGIC; -- asynchronous, active-low reset for controller
           --invDRst_in : in  STD_LOGIC; -- asynchronous, active-low reset for DAC
           invTxGo : in  STD_LOGIC; -- active-low start of transmission pulse
           Addr : in  STD_LOGIC_VECTOR (4 downto 0); -- 5-bit address
           Code : in  STD_LOGIC_VECTOR (13 downto 0); -- 14-bit code
           --SCLK : out  STD_LOGIC; -- SCLK
           invSYNC : out  STD_LOGIC; -- /SYNC
           Data : out  STD_LOGIC; -- D_in
           --invDRst_out : out  STD_LOGIC; -- /RESET
			  Done : out STD_LOGIC );
end DAC_controller;

architecture DAC_control_arch of DAC_controller is

	-- declaring component wrappers
	component c_delay
		Port (	CLK		:	in		STD_LOGIC;
					D			:	in		STD_LOGIC;
					Q			:	out	STD_LOGIC);
	end component;

	component Pulser
		Port (	CLK		:	in		STD_LOGIC;
					D			:	in		STD_LOGIC;
					Q			:	out	STD_LOGIC);
	end component;

	component DAC_hold19
		Port (	CLK		:	in		STD_LOGIC;
					invReset	:	in		STD_LOGIC;
					invBegin	:	in		STD_LOGIC;
					Go			:	out	STD_LOGIC);
	end component;
	
	component DAC_shiftreg
		Port (	CLK		:	in		STD_LOGIC;
					invRST	:	in		STD_LOGIC;
					Addr		:	in		STD_LOGIC_VECTOR (4 downto 0);
					Code		:	in		STD_LOGIC_VECTOR (13 downto 0);
					Sh_iRd		:	in		STD_LOGIC;
					Q			:	out 	STD_LOGIC);
	end component;
	
	signal shift : STD_LOGIC;
	signal ishift : STD_LOGIC;
	signal Done_shift : STD_LOGIC;
	signal invSync_int : STD_LOGIC;
	--signal iGo_hold : STD_LOGIC;

	signal Addr_int : STD_LOGIC_VECTOR (4 downto 0);
	signal Code_int : STD_LOGIC_VECTOR (13 downto 0);

begin

--	LatchData : process (Clk, invTxGo)
--	begin
--		if (invRst='0') then
--			Addr_int <= "00000"; 	Code_int <= "00000000000000";
--		else
--			if falling_edge(Clk) then
--				if (invTxGo='0') then
--					Addr_int <= Addr;		Code_int <= Code;
--				end if;
--				iGo_hold <= invTxGo;
--			else
--				Addr_int <= Addr_int; Code_int <= Code_int; iGo_hold <= iGo_hold;
--			end if;
--		end if;	
--	end process;
	
	
	-- port maps to include components
	u1: DAC_hold19		port map (CLK, invRst, invTxGo, shift);
	u2: DAC_shiftreg	port map (CLK, invRst, Addr, Code, shift, Data);
	u3: c_delay			port map (CLK, invTxGo, invSync_int);
	invSync <= invSync_int;
	
	-- Done signal
	ishift <= not shift;
	u4: Pulser        port map (CLK, ishift, Done_shift);
	u5: c_delay       port map (CLK, Done_shift, Done);

	-- (uncomment if not wired by FPGA_ctrl)
	-- connect feed-through signals
	--SCLK <= CLK;
	--invDRst_out <= invDRst_in;

end DAC_control_arch;