----------------------------------------------------------------------------------
-- Company: University of Connecticut
-- Engineer: Igor Senderovich
-- 
-- Create Date:    12:14:27 10/28/2009 
-- Module Name:    ConfigParam - Behavioral 
-- Description:    FPGA firmware fixed parameter file
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity ConfigParam is
    Port ( DAC_Qmax : out  STD_LOGIC_VECTOR (13 downto 0);
           dbShort  : out  STD_LOGIC);
end ConfigParam;

architecture Behavioral of ConfigParam is
begin

	-- IMPORTANT: the following sets the maximum allowed
	-- DAC output voltage. Conversion from voltage units:
	--   DAC_Qmax = Vmax * 2^14/(Vref*50)
	-- original board design: Vref=3.3V
	DAC_Qmax <= "00111111100111"; -- = 41V @ Vref=3.3V


	-- shorts out the mandatory long waiting times when set to '1'
	-- e.g. during Eth. Ctrl physical layer startup
	-- Used only as a convenience for simulations.
	dbShort <= '0';

end Behavioral;